• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.199-206
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• 2016

This paper describes a simple routing control system. We propose achieving high-speed data transmission without modifying the data frame configuration. To add a routing control signal, called the "labeling signal" in this paper, to the data frame, we use a frequency modulation technique on the transmitted frame. This means you need not change the data frame when you transmit additional signals. Using a prototype system comprising a field-programmable gate array and discrete elements, we investigate the system performance and devise a method to achieve high resolution. A three-channel routing control for a 10 Gb/s data frame was achieved, which confirms the advantages of the proposed system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.3
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• pp.128-132
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• 2006

The previous MCCs(Motor Control Centers) have the demerits of high cost and much manhour for rework because it is impossible for us to standardize the previous MCCs and they have many manual connections. The customers require the products which can operate with the SCADA system by digitalizing the functions of the current MCCs and the systematized products with capability of remote control. To solve these disadvantages and requirements, we developed the Intelligent Motor Control Center. This system has the various functions such as protection, measuring, and communication. Using these functions, we can monitor motor status through communication with the upper system and define the circuit for lowering connection costs according tn starting type and shortening the manufactural period by the graphic editor. The development of this system results in establishment of the competitive structure with domestic area and Perfect automatic monitoring through linkage with the SCADA system.

• The Bulletin of The Korean Astronomical Society
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• v.40 no.2
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• pp.44.1-44.1
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• 2015

We set up a project to make spectrometers for single dish observations of the Korean VLBI Network (KVN), a new future multi-beam receiver of the ASTE (Atacama Submillimeter Telescope Experiment), and the total power (TP) antennas of the Atacama Large Millimeter/submillimeter Array (ALMA). Traditionally, spectrometers based on ASIC (Application-Specific Integrated circuit) and FPGA (Field-Programmable Gate Array) have been used in radio astronomy. It is, however, that a Graphics Processing Unit (GPU) technology is now viable for spectrometers due to the rapid improvement of its performance. A high-resolution spectrometer should have the following functions: poly-phase filter, data-bit conversion, fast Fourier transform, and complex multiplication. We wrote a program based on CUDA (Compute Unified Device Architecture) for a GPU spectrometer. We measured its performance using two GPU cards, Titan X and K40m, from NVIDIA. A non-optimized GPU code can process a data stream of around 2 GHz bandwidth, which is enough for the KVN spectrometer and promising for the ASTE and ALMA TP spectrometers.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1798-1799
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• 2011

In this paper, A new cost-effective and accurate input noise rejection method for High Speed Counter module of PLC (Programmable Logic Controller) is proposed. By using combination of simple additional logic circuit and the Timer Pulse function of general purpose MPU, Cost-effectiveness and improvement of accuracy of filtering function can be achieved. This proposed method is verified by simulation. This proposed method is much useful for simple industrial controller based on simple microprocessor because of simplicity, accuracy and low cost.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.283-285
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.169-170
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• 2012

This paper presents implementation of digital phase controller for thyristor by using FPGA (Field Programmable Gate Array) in HVDC system. Implementation of digital HVDC system is possible by using superior digital simulator such as RTDS (Real Time Digital Simulator). But thyristor phase controller is typically implemented by analog circuit, because it is difficult to implement the phase controller with low operating speed of RTDS. To guarantee high control performance, phase controller needs fast operating speed. This paper presents FPGA based digital phase controller to obtain high speed and high performance. The entire digital simulation of the HVDC system is also implemented by interfacing between FPGA based phase controller and RTDS. Proposed digital HVDC simulator is verified through RTDS simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1839-1849
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• 1989

An optimal variable assignment algorithm is presented as a decomposition method of MVL functions. A given 3-valued combinational logic function is disintegrated into subfunction composed of the function dependant relation, then extracted implicant output elements from subfunctions are assigned to a T-gates. As a circuit implementation tool, a programmable integarated T-gate module is proposed, and the construction procedure of combinational MVL functions is systematized in each step. This method is expected to give properties of the systematic procedure, possibility of T-gate number reduction, unification of module, and flexibility of module composition. Specially variable decomposition method can be pointed out as an approach to solving the limitation problem of the input and output terminal number in VLSI implementations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.438-441
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• 2000

In this paper, Turbo rode is describing a performance near the Shannon's channel capacity limit. So, basic theory of turbo code and MAP,Log-MAP decoding algorithm was arranged. The foundation of this using VHDL, Log-MAP turbodecoder was implemented by Altera´s FLEX10K CPLD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.673-675
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• 2011

본 논문은 GHz 대역 소자 응용을 위한 프로그램 가능 보상 회로를 제안한다. 이러한 회로는 5.2GHz대에서 동작하는 고주파 회로의 칩 제작과정에서 예기치 않게 발생한 미세한 PVT (공정, 전압, 온도) 변동을 검출하여 미세 변동된 회로 성능 변수들을 자동으로 보상한다. 자동으로 보상 가능한 고주파 회로 성능 변수들은 중요한 요소인 입력 임피던스, 전압이득과 잡음지수를 포함한다. 이러한 회로는 미세 변동을 자동으로 보상할 수 있도록 고주파 신호를 직류 신호로 변환하는 DFT (Design-for-Testability) 회로를 포함한다.