• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.563-566
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• 2003

We have designed the power control unit which belongs to the power cabinet and controls the power supplied to Control Rod Drive Mechanism(CRDM) as a digital system based on Digital Signal Processor(DSP). The power control unit dualized as the form of Master/Slave has had its increased reality. The Central Process Unit(CPU) board of a power control unit possesses two Digital Signal Processors(DSPs) of the control DSP for performing the tasks of power control and system monitoring and the communication of the Control DSP and the Communication DSP. To accomplish the functions requested in the power control unit effectively, we have installed Field Programmable Gate Arrays(FPGAS) on the CPU board and have FPGAs perform the memory mapping, the generation of each chip selection signal, the giving and receiving of the signals between the power controllers dualized, the fault detection and the generation of the firing signals.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.61-70
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• 2007

The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

• Journal of Magnetics
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• v.16 no.4
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• pp.363-367
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• 2011

We have designed, fabricated and demonstrated a novel micro-system for programmable magnetic actuation using magnetic elliptical pathways on Si substrates. Lithographically patterned soft NiFe ellipses are arranged sequentially perpendicular to each other as stepping stones for the transport of magnetic beads. We have measured the magnetization curve of the ellipsoid ($9\;{\mu}m{\times}4\;{\mu}m{\times}0.1\;{\mu}m$) elements with respect to the long and short axes of the ellipse. We found that the magnetization in the long axis direction is larger than that in the short axis direction for an applied field of ${\leq}$ 1,000 Oe, causing a force on carriers that causes them to move from one element to another. We have successfully demonstrated a micro-system for the magnetic actuation of biomolecule carriers of superparamagnetic beads (Dynabead$^{(R)}$ 2.8 ${\mu}m$) by rotating the external magnetic field. This novel concept of magnetic actuation is useful for future integrated lab-on-a-chip systems for biomolecule manipulation, separation and analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.2
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• pp.97-104
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• 2011

This paper deals with the quick and precise disaster prevention automation system (DPAS) based on information communication technology (IT) that detects fire and disasters in the building automatically and quickly and then activates the facilities to extinguish fire and disasters, monitoring such situation in a real time through wire-wireless communication network. The proposed DPAS is applied a programmable logic controller (PLC) of one-chip type which is smallsize and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLC analyzes detected signals from sensors in a case of fire and disasters, then activates fire extinguishing facilities for rapid suppression. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication. The transferred data sounds an emergency alarm signal, and operates a monitoring program. The proposed DPAS based on IT will minimize the life and wealth loss from rapid measures while prevents fire and disasters.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.462-469
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• 2008

In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2843-2845
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• 2005

This paper deals with the design of real-time embedded system using RTOS (real-time operating system) and SOPC (system on a programmable chip). It is, in general, known that RTOS has the problem of time delay caused by the multiple tasks and task management approach. Since the increase in time delay in real-time embedded system makes the overall system have the poor performance or the critical behavior of instability and unreliability, the method employed RTOS and SOPC is proposed to attack the above problems. The proposed system is implemented on the RC-motor controller and is verified by real experiment.

• Journal of The Korean Astronomical Society
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• v.29 no.spc1
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• pp.389-390
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• 1996

The CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However, the areas of available sensors are too small for large imaging format. One possibility to obtain large detection area is to assemble mosaics of CCD, and drive them simultaneously. Parallel driving of many CCDs together rules out the possibility of individual tuning; however, such optimisation is very important, when the ultimate low light level performance is required, particularly for new, or mixed devices. In this work, a new concept is explored for an entirely novel approach, where the drive waveforms are multiplexed and interleaved. This simultaneously reduces the number of leadout connections and permits individual optimisation efficiently. The digital controller can be designed within a single EPLD (Erasable Programmable Logic Device) chip produced by a CAD software package, where most of the digital controller circuits are integrated. This method can minimise the component. count., and improve the system efficiency greatly, based on earlier works by Han et a1. (1996, 1994). The system software has an open architecture to permit convenient modification by the user, to fit their specific purposes. Some variable system control parameters can be selected by a user with a wider range of choice. The digital controller design concept allows great flexibility of system parameters by the software, specifically for the compatibility to deal with any number of mixed CCDs, and in any format, within the practical limit.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.107-108
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• 2010

Uncertainty and insecurity is a serious issue in all aspects of our society today as the change in environmental and societal conditions became more apparent than ever before through various disasters. Thus, it is now an important point in time for the government and responsible firms to implement an innovative scientific disaster management method that can lead to establishing a more secure and stable future. Therefore, authors have developed ubiquitous- based disaster prevention automation system(DPAS). The system would follow up after sensors detecting fires, thefts, torrents, floods, and infrastructural leaks. It prevents disasters in advance by utilizing a wireless communications net or ethernet to conduct real-time monitoring from a remote place. The system also has an advantage as it is designed in a compact size that applies a precision-focused programmable logic controller(PLC) of one-chip type.

• Nuclear Engineering and Technology
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• v.54 no.11
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• pp.3985-3995
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• 2022

The emergence of new nanoscale technologies has imposed significant challenges to designing reliable electronic systems in radiation environments. A few types of radiation like Total Ionizing Dose (TID) can cause permanent damages on such nanoscale electronic devices, and current state-of-the-art technologies to tackle TID make use of expensive radiation-hardened devices. This paper focuses on a novel and different approach: using machine learning algorithms on consumer electronic level Field Programmable Gate Arrays (FPGAs) to tackle TID effects and monitor them to replace before they stop working. This condition has a research challenge to anticipate when the board results in a total failure due to TID effects. We observed internal measurements of FPGA boards under gamma radiation and used three different anomaly detection machine learning (ML) algorithms to detect anomalies in the sensor measurements in a gamma-radiated environment. The statistical results show a highly significant relationship between the gamma radiation exposure levels and the board measurements. Moreover, our anomaly detection results have shown that a One-Class SVM with Radial Basis Function Kernel has an average recall score of 0.95. Also, all anomalies can be detected before the boards are entirely inoperative, i.e. voltages drop to zero and confirmed with a sanity check.