• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.253-256
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• 2002

A programmable CMOS negative resistor has been designed and fabricated in a 0.5um double poly double metal technology. The proposed CMOS negative resistor consists of a positive feedback OTA and a bump circuit with Gaussian-like I-V curve. Measurements of the fabricated chip confirm that the proposed CMOS resistor shows various negative resistance according to control voltage.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.345-350
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• 2019

This study deals with the design of a modular converter that can convert the output voltage according to the size of the load. The efficiency of the converter depends on the size of the load and is generally less efficient for lower loads. Therefore, it is more efficient to construct a small capacity modular converter than to manufacture a large capacity converter and it determines the capacity of the system through the parallel connection of the converter module according to the load size. In this paper, we will introduce a modular DC / DC converter designed to control the number of modules according to the load. A programmable resistor is placed at the output of the module for parallel connection of the module, and the voltage is regulated by adjusting the variable resistor. A system controlled in this way was found to exhibit an efficiency improvement of about 32%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.198-206
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• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• Proceedings of the KIEE Conference
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• 1998.07b
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• pp.423-425
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• 1998

In this paper, a novel Programmable Signal Conditioner(PSC) for Thermo Couple(T/C) without variable-resistance is proposed. It is fabricated by using a fully digitalized error-correction and calibration algorithm. In signal processing of T/C, since the output voltage of T/C is nonlinear and its level is very low, the circuitry become very complicated to reduce the converting error and identify the true thermal voltage signal. The newly proposed PSC has compensation and calibration algorithm not using variable resistor. Moreover structure can be very simple and it has highly precise output characteristics.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.43-55
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.6
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• pp.699-706
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• 2015

A previous adapter have a single-ouput, however, a demand of a multi-output adapter increase in the recent industrial site. In order to satisfy the demand, in this research, we implement a programmable high efficiency multi-output adapter. The basic structure of the adapter introduced in this paper is a sort of flyback. The way for producing the reference voltage of the adapter proposed is similar to the way in the general flyback implemented with TL431. In addition to the basic concept of the design, however, we introduce a digital variable resistor, AD5246BKSZ10-RL7 and a microcontroller for changing a programmable multi-output. It makes output be variable that the digital variable resistor change the reference voltage of the adapter by order of the microcontroller. The adapter output voltage is controllable in the range of 20V by the user, and the power efficiency is proven to be 85%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.172-178
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• 1986

The recent interest in the design of filters is motivatied by the fact that such filter can be fully integrated using standard metal-oxide-semiconductor processing technology. This is due to replacing all the resistors in the active RC filter network by the switched capacitors. The voltage gain of a SC filter depends only on the rations of capacitance and these ratios can be obtained and maintained to high accuracy. Therefore, it is known that a switched capacitor is much better than a resistor in temperature and linearity characteristics. This paper proposed a programmable SC filter and proved the fact that ${omega}_0$ Q and G of this circuit can be controlled by digital signal. Experiments show that SC filter remains the low sensitivities but it can't avoid little influence of parasitic capacitance. As the transfer characteristic of the SC filter is varied with sampling frequency and resistor array, SC filtering technigue can be applied for digital processing, speech analysis and synthesis and so on.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.349-351
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• 2013

This research paper presents a low-power programmable gain amplifier (PGA) to facilitate signal processing of the detection of defects in steel plates. This circuit is able to adjust a gain in the range of 6 to 60dB in 7 steps using different signal types for various defects from hall sensors. The gain of PGA is designed by operating on-resistors of switches and passive components. The proposed PGA ($0.18{\mu}m$ CMOS process with 1.8 supply voltage) showed excellent gain error of less than -0.2dB, and low power consumption of 0.47mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.