• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.706-714
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• 2008

In this paper, we suggest a practical and flexible system architecture for JTAG(Joint Test Action Group) protection of application processors. From the view point of security, the debugging function through JTAG port can be abused by malicious users, so the internal structures and important information of application processors, and the sensitive information of devices connected to an application processor can be leak. This paper suggests a system architecture that disables computing power of computers used to attack processors to reveal important information. For this, a user authentication method is used to improve security strength by checking the integrity of boot code that is stored at boot memory, on booting time. Moreover for user authorization, we share hard wired secret key cryptography modules designed for functional operation instead of hardwired public key cryptography modules designed for only JTAG protection; this methodology allows developers to design application processors in a cost and power effective way. Our experiment shows that the security strength can be improved up to $2^{160}{\times}0.6$second when using 160-bit secure hash algorithm.

• The Journal of the Acoustical Society of Korea
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• v.19 no.7
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• pp.42-47
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• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• Journal of the korean academy of Pediatric Dentistry
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• v.25 no.3
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• pp.513-524
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• 1998

The purpose of this study was to compare the staining ratio on the enamel surface following the use of chlorhexidine mouthwash and the chlorhexidine varnish application. Labial and lingual surfaces of maxillary and mandibular incisors of adults were selected to evaluate the staining ratio. The control group was consisted of 8 individuals, the experimental group 1 and 2 were consisted of 50 each. Prophylaxis with pumice was performed to remove the stain already established on the enamel surface of all groups. The group 1 was asked to use chlorhexidine mouthwash(Hexadent, chlorhexidine gluconate 1ml/100ml) for a minute twice a day. The chlorhexidine $varnish^{(R)}$($Chlorzoin^{(R)}$, consisted of solution 1(10% chlorhexidine acetate) and solution 2(polyurethane sealant)) was applied on the enamel surfaces of the group 2. After 4 weeks of experiment, intraoral photogragh of tooth surfaces were taken in order to record the stained area on the enamel of the control and the experimental groups. Outline of teeth and the stained area in the photographs was traced on the OHP film. Scanner and computer processor were used to calculate stained surface ratio.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.34-36
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• 2002

This paper addresses an elevator position control scheme in unified control system. Conventional systems have employed independent micro-processors for speed, car, and group control respectively and the car controller generates a velocity command by combining the time-based and distance-based velocity pattern. In this scheme, it is inevitable that an elevator creeps in the vicinity of target floor, or stops abruptly. The proposed control system employs only one high-performance micro-processor, which can execute the car and group control as well as the speed control. It simply generates the desired position trajectory based on time and on-line corrects a velocity pattern to make the position error be zero. Experimental results show the feasibility of the proposed control scheme.

• Journal of Power Electronics
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• v.15 no.2
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• pp.518-529
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• 2015

Repetitive and proportional-resonant controllers can effectively reject grid harmonics in grid-connected inverters because of their high gains at the fundamental frequency and the corresponding harmonics. However, the performances of these controllers can seriously deteriorate if the grid frequency deviates from its nominal value. Non-ideal proportional-resonant controllers provide better immunity to variations in grid frequency by widening resonant peaks at the expense of reducing the gains of the peaks, which reduces the effectiveness of the controller. This paper proposes a repetitive control scheme for grid-connected inverters that can track changes in grid frequencies and keep resonant peaks lined up with grid frequency harmonics. The proposed controller is implemented using a digital signal processor. Simulation and practical results are presented to demonstrate the controller capabilities. Results show that the performance of the proposed controller is superior to that of a proportional-resonant controller.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1714-1719
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• 2003

Antilock Brake System (ABS) is indispensable safety equipment for vehicles today. In order to develop new ABS ECU suitable for pneumatic brake system of a bus, a Hardware In-the-Loop Simulation (HILS) System was developed. In this HILS, the pneumatic brake system of a bus and antilock brake component were used as hardware. For the computer simulation, the 14-Degree of Freedom (DOF) bus dynamic model was constructed using the Matlab/Simulink software package. This model was compiled and downloaded in the simulation board, where the Power PC processor was used for real-time simulation. Additional commercial package, the ControlDesk was used to monitor the dynamic simulation results and physical signal values. This paper will focus on the procedure and results of evaluating the ECU in the HILS simulation. Two representative cases, wet basalt road and $split-{\mu}$ road, were used to simulate real road conditions. At each simulated road, the vehicle was driven and stopped under the help of the developed ECU. In each simulation, the dynamical behavior of the vehicle was monitored. After enough tests in the laboratory using HILS, the parameter-tuned ECU was equipped in a real bus, which was driven and stopped in the real test field in Korea. And finally, the experiment results of ABS equipped vehicle's dynamic behavior both in HILS test and in test fields were compared.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.25-37
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• 1996

To process computer graphics in real time, the high-speed operations(multiplier and adder) are needed to increase the speed of graphic process. RNS(Residue Number System) is integer number system that has the parallel and high-speed operation. Also, it is able to design both high-speed multiplier and adder, since a cyclic group has an isomorphic relation between multiplication and addition in RNS. So in this paper, DRNS(Double Residue Number System) is proposed, it is used for the multiplier and the adder, which are designed using a circulative code for the high-speed graphic processor in RNS. The designed multiplier would operate with the speed of 87Mzz two TTL using 74s09 and 74s32.

• Journal of KIEE
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• v.10 no.1
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• pp.35-42
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• 2000

An equivalent load sharing control based on the frequency and voltage droop concept for parallel operation of two three-phase Uninterruptible Power Supply (UPS) systems with no control interconnection lines is presented in this paper. First of all, due to the use of active power and reactive power as control variables, the characteristics of output powers according to amplitude and phase differences between output voltages of two UPS systems are analyzed. Secondly, simulation results under different line impedance demonstrate the feasibility of the wireless parallel operation control. Finally, experiments are presented to verify the theoretical discussion with two three-phase 20kVA UPS systems employed TMS320C32, a kind of real time digital signal processor (DSP).