• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.279-282
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• 2002

In this paper, we present a new method for monitoring of ECU's self diagnostic signals of vehicle without wire. In order to measure the ECU's self diagnostic signals, the interfaced circuit is designed to communicate ECU and a designed display terminal according to the ISO, SAE regulation of communication protocol standard. A 80C196KC processor is used for communicating ECU's self diagnostic signals and the results are sent to PDA monitoring system. Software on PDA is developed to monitor the ECU's self diagnostic signals using the Embedded Visual C++ compiler in which RS232 port is programmed by half duplex method. The algorithms for measuring the ECU's self diagnostic signals are verified to monitor ECU's state. At the same time, the information to fix the vehicle's problem can be shown on the developed PDA software. The possibility for remote measurement of ECU self diagnostic signal using PDA is also verified through the developed systems and algorithms.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.5
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• pp.159-167
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• 2002

In this paper. we present a new method for monitoring of ECU's self diagnostic signals of vehicle without wire. In order to measure the ECU's self diagnostic signals, the interfaced circuit is designed to communicate ECU and designed terminal according to the IOS, SAE regulation of communication protocol standard. Micro-processor 80C196KC is used for communicating ECU's self diagnositc signals and the results are sent to the wireless terminal and PC monitoring system. Wireless terminal is also developed by 80C196KC, LCD, RF module, and keypad. The command from the keypad is sent to ECU through RF module and the result show on the Graphic LCD in real time. Software on PC is developed to monitor the ECU's self diagnostic signals using the Visual C++ complier in which RS232 port is programmed by half duplex method. The algorithms for measuring the ECU's self diagnostic signals are verified to monitor both ECU and portable terminal state. At the same time, the information to fix the vehicle's problem can be shown on the developed software. The possibility for remote measurement of ECU self diagnostic signal is verified through the developed systems and algorithms.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.339-342
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• 2005

In order to support ultrawide-band signal generation for low rate WPAN, several types of signal generation mechanisms are suggested such as Chaos, Impluse, and Chirp signals by the activity of IEEE 802.15.4a. The communication system applied chaos theory may have ultrawide-band characteristics with spread spectrum and immunity from multipath effect. In order to use the advantage of chaotic signal generation, we introduce the system implementation of communication and networking systems with the chaos UWB signal. This system may be composed of mainly three parts in hardware architecture : RF transmission with chaotic signal generation, signal receiver using amplifiers and filters, and 8051 & FPGA unit. The most difficult part is to implement the chaotic signal generator and build transceiver with it. The implementation of the system is devidced into two parts i.e. RF blocks and digital blocks with amplifiers, filters, ADC, 8051 processor, and FPGA. In this paper, we introduce the system block diagram for chaotic communications. Mainly the RF block is important for the system to have good performance based on the chaotic signal generator. And the main control board functions for controlling RF blocks, processing Tx and Rx data, and networking in MAC layer.

• Journal of information and communication convergence engineering
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• v.14 no.3
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• pp.177-183
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• 2016

A lot of Internet of Things devices has resource-restricted environment, so it is difficult to implement the existing block ciphers such as AES, PRESENT. By this reason, there are lightweight block ciphers, such as SIMON, SPECK, and Simeck, support various block/key sizes. These lightweight block ciphers can support the security on the IoT devices. In this paper, we propose efficient implementation methods and performance results for the Simeck family block cipher proposed in CHES 2015 on an 8-bit ATmega128-based STK600 board. The proposed methods can be adapted in the 8-bit microprocessor environment such as Arduino series which are one of famous devices for IoT application. The optimized on-the-fly (OTF) speed is on average 14.42 times faster and the optimized OTF memory is 1.53 times smaller than those obtained in the previous research. The speed-optimized encryption and the memory-optimized encryption are on average 12.98 times faster and 1.3 times smaller than those obtained in the previous studies, respectively.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.4
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• pp.467-475
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• 2016

Ultrasonic propagation imaging (UPI) has shown great potential for detection of impairments in complex structures and can be used in wide range of non-destructive evaluation and structural health monitoring applications. The software implementation of such algorithms showed a tendency in time-consumption with increment in scan area because the processor shares its resources with a number of programs running at the same time. This issue was addressed by using field programmable gate arrays (FPGA) that is a dedicated processing solution and used for high speed signal processing algorithms. For this purpose, we need an independent and flexible block of logic which can be used with continuously evolvable hardware based on FPGA. In this paper, we developed an FPGA-based ultrasonic propagation imaging system, where FPGA functions for both data acquisition system and real-time ultrasonic signal processing. The developed UPI system using FPGA board provides better cost-effectiveness and resolution than digitizers, and much faster signal processing time than CPU which was tested using basic ultrasonic propagation algorithms such as ultrasonic wave propagation imaging and multi-directional adjacent wave subtraction. Finally, a comparison of results for processing time between a CPU-based UPI system and the novel FPGA-based system were presented to justify the objective of this research.

• Proceedings of the Korea Contents Association Conference
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• 2006.05a
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• pp.479-482
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• 2006

Mobile Telemedicine uses common technologies that provide a conduit for information exchange between physicians nurses and patients. In addition to patient records, medical professionals will obtain vital signs and other reference data through Ubiquitous Sensor networks(USN). In this paper about a design and implementation of RFID reader platform that received RFID tag information from patients tags, transmit the data to SBC(Single board computer) based on Intel PXA255 ARM CPU and SBC transmit the data to MySQL server in hospital using by Wireless Internet. his system that based on Embedded Linux is composed of RFID module, ARM processor, RS-232 interface, and Wireless LAN. This paper also provides a brief overview and concept of RFID reader, and proposes the design and implementations of the RFID reader platform used QT and MySQL based on Embedded Linux.

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1460-1470
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• 2008

As the performance of recent mobile systems increases, a vector graphic has been implemented to represent various types of dynamic menus, mails, and two-dimensional maps. This paper proposes a hardware accelerator for open vector graphics (OpenVG), which is widely used for two-dimensional vector graphics. We analyze the specifications of an OpenVG and divide the OpenVG into several functions suitable for hardware implementation. The proposed hardware accelerator is implemented on a field programmable gate array (FPGA) board using hardware description language (HDL) and is about four times faster than an Alex processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.126-133
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• 2006

This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.39-46
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• 2004

This paper presents the realization schemes for a multipurpose coherent mono-pulse radar Simulator with extendable features. We developed and installed the TSG(Timing Signal Generator) board which can simulate a mechanically rotate signal of antenna, an operation timing signal of pulse radar and target signal, to operate the simulator without real target in the indoor environment. Also, with the insertion of the radar signal processor, it came to be easy to achieve the addition of radar function algorithms, to rebuild or extend the multi-DSP Architecture into the simulator. Throughout the simulation results, we verified that the designed coherent mono-pulse radar simulator can exactly display a moving target on the realistic monitor(RD 9800).

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.361-363
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• 2005

본 논문에서는 MPEG-4 Version2 Audio 표준에 근거하여 낮은 연산부담을 갖는 독자적인 엘고리즘을 적용한 MPEG-4 BSAC Audio 디코더를 개발하였다. 개발된 BSAC 디코더는 32bit RISC 구조를 갖는 Intel Xscale Processor 기반 시스템에 최적화하여 구현 및 평가를 수행하였다. 수행속도 증가 및 연산 정밀도 향상을 위해 각 기능 블록별 기능 및 구현 원리 연구와 32 bit 연산 구조를 파악하여, 이를 고정소수점 연산 구조로 구현함으로써 성능을 향상시켰다. 유한비트에 따른 오차 영향을 최소화하기 위해 데이터의 표현 범위에 대한 연구를 통해 근사한 오차를 최소화 하여 연산 정밀도를 향상 시키고자 하였다. 비선형 양자화기 및 filter bank 등 상대적으로 높은 연산 부담을 갖는 기능 블록은 Table look-up, 보간법, 지수연산 제거, pre/post scrambling 기법 등을 적용하여 최적화 하였다. 최종적으로 개발된 BSAC 디코더는 32 bit 연산 구조의 X-scale 프로세서를 탑재한 Development Board와 WindowsCE OS로 구성된 타겟 system에 이식하여 performance 평가하였으며, 높은 연산 정밀도 및 다른 수행속도를 확인할 수 있었다. 주관적인 청각 평가에서도 MPEG-4 reference 디코더와의 음원의 차이가 거의 없음을 확인하였다.