• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.61-66
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• 1992

In this paper, a method for implementing software for the control system with dual structure in processor module is proposed and implemented to enhance its reliability. In this implementation the multi-tasking function which is provided by a real-time operating system is applied. The overall softwre is divided into five tasks and is performed in each of the dual processor module, independently. By this, the processor module with dual structure can achieve a control objective and fault diagnostics effectively. An experimental result shows that the backup processor module can be substituted for the primary processor module immediately when it happens to fail, because data relating the failure information are exchanged continuously done via shared memories.

• 한국정밀공학회지
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• 제17권5호
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• pp.116-123
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• 2000

This paper presents an NC code post-processor that adjusts feedrates to keep the variation of metal removal rate along the tool paths minimum. Metal removal rate is estimated by virtually machining the part, whose surface model is built from a series of NC codes defined in operation plan, with cutting-tool-assembly models, whose geometry are defined in a machining database. The NC code post-processor modifies the feedrates by the adjustment rules, which are based on the machining knowledge for effective machining. This paper illustrates a procedure fur grouping machining conditions and we also show how to determine an adjustment rule for a machining-condition group. An example part was machined and it shows that the variation of cutting force was dramatically reduced after applying the NC code post-processor. The NC code post-processor is expected to increase productivity while maintaining the quality of the machined part.

• 한국통신학회논문지
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• 제26권9B호
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• pp.1308-1313
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• 2001

It is essential design process to analyze processing load and set up top level software and hardware mapping using main parameters before implementation of the SAR processor. This paper identifies the requirements upon the software and hardware mapping to be assessed and suggests its practical method to the SAR processor. Also, simulation is performed to the E-SAR processor to examine the practicability of the method and the results are discussed. Thus, this method can be applied to the SAR processor.

• 한국통신학회논문지
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• 제27권7B호
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• pp.737-743
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• 2002

It is an essential design process to analyze the performance of Synthetic Aperture Radar (SAR) processor before implementation. The contribution of this paper is to identify the chief sources and types of errors, to assess their impact on system performance, and to suggest the analysis technique for principal performance of the space-based SAR processor using Range-Doppler Algorithm (RDA). Also, simulation is performed by the Experimental-SAR (E-SAR) processor to examine the practicability and efficiency of the technique, the results are discussed, and solutions for the problems are recommended. Therefore, this technique can be used to analyze the performance of the space-based SAR processor using RDA.

• ETRI Journal
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• 제32권1호
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.651-652
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• 2006

In this paper, 4-way data path 128 point pipelined FFT processor with 4-way structure is proposed. The proposed FFT processor has 4-way structure in order to meet data requirement of MB-OFDM system at 132MHz operating frequency. The FFT processor is based on R4MDC and extended to suit 4-way data path. The FFT processor is designed by Verilog HDL and the gate count is about 88k.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• 한국전자통신학회논문지
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• 제4권4호
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• pp.287-292
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• 2009

u-City 사업은 도시개발 프로세서와 IT 사업 프로세서가 결합된 구축 프로세서로 도시개발 계획 단계에서 u-City 계획 및 설계 내역이 반영되어야 효율적으로 구축이 가능하며, 비용 절감을 할 수 있다. 본고에서는 도시개발 프로세서와 u-City 사업 프로세서 간 연계방안을 제시하고 각 단계별 주요업무를 설정하여 제시하였으며, 특히 도시개발 프로세서와 연계한 u-City 사업을 성공적으로 이끌기 위한 단계별 핵심 업무 중 USP(u-City Strategic Planning)수립 방안들에 대하여 고찰하고자 한다.

• 전자공학회논문지B
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• 제30B권7호
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• 한국철도학회논문집
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• 제5권2호
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• pp.55-60
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• 2002

This study proposes the post-processor simulator construction of ultrasonic signal for integrity evaluation of railway truck. For these purposes, the ultrasonic signals for defects(crack) of weld zone in frames are acquired in the type of time series data and echo strength. The detection of the natural defects in railway truck is performed using the characteristics of echodynamic pattern in ultrasonic signal. The constructed post-processor simulator agree fairly well with the measured results of test block(defect location, beam propagation distance, echo strength, etc). Proposed post-processor simulator construction of ultrasonic in this study can be used for the integrity evaluation of railway truck.