• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2001년도 The Seoul International Simulation Conference
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1190-1194
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• 2007

Since the dismantling processes of building are very dangerous, there have been many studies to develop a remote operating devices using joystick. In this paper, in order to improve the operability of the dismantling actuator that is usually an excavator, a novel concept of tele-operated haptic device is proposed. Operators who use this haptic device with additional environmental sensing devices can work safely away from the dangerous sites. First, based on the concept design of the haptic device, the workspace mapping from the haptic device to the excavator is explored. Second, the kinematics which deals with the conversion from the 3 dimensional position information of the haptic device to the joint variable information of the backhoe is included. Lastly, 3D graphical simulation of both haptic device and the backhoe will be shown. This new design of the haptic device can be easily manufactured and gives the workers very convenient and transparent remote control capability.

• 문화기술의 융합
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• 제8권3호
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• pp.477-483
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• 2022

비행 시뮬레이터는 조종사들이 다양한 상황에 능숙하게 대처하고 비행감을 느낄 수 있도록 해주는 장치로 현대 항공 분야에서 과학화 훈련에 관한 관심이 증가함에 따라 항공 훈련기관에서는 시뮬레이터를 개발 및 운용하는 사례가 증가하고 있다. 이에 본 연구에서는 상용 비행 시뮬레이터 프로그램과 모션 프로그램을 활용하여 모션 기반 헬리콥터 시뮬레이터를 개발하는 과정에 관하여 기술하였다. 연구 과정에서 선행연구를 통하여 헬리콥터 비행교육의 특수성과 모션 시뮬레이터의 긍정적인 효과를 확인하였으며, 모의비행훈련장치에 대한 구성과 현행 규정을 파악하고 헬리콥터 모션 시뮬레이터를 개발하는 과정에서 모션 시스템의 설계와 프로그램에 관하여 연구하였다. 시뮬레이터의 시스템 설계와 구조설계를 바탕으로 모션 프로그램을 설정하고 비행 시뮬레이터로부터 수신되는 데이터를 식별하여 예상 작동 형상을 확인하였다. 우리는 본 연구를 통해 모션 기반 헬리콥터 시뮬레이터를 완성하여 조종사 훈련에 긍정적인 기대효과를 마련하고자 한다.

• 한국세라믹학회지
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• 제43권12호
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• pp.859-864
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• 2006

For the pressure compaction process of the ceramic powder, the green density is very different with both the ceramic body shape and the processing conditions. The density difference cause non-uniform shrinkages and deformations, and make cracks in the sintered ceramics. In this paper, Material properties of the alumina powder mixed with binder and the friction coefficient between the powder and the tool set were determined through the simple compaction experiments: Also the powder flow characteristics were simulated and the green density was analyzed during the powder compaction process with Finite Element Method (FEM). The results show that the density distributions of the green body were improved at the optimized processing condition and both the possibility of the farming crack generation and rho deformation of the sintered Alumina body were reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.370-376
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• 2012

In this work, design considerations for high-performance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An $f_{-3dB}$ of 80 GHz at an operating voltage of 1 V was obtained.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

• 한국전기전자재료학회논문지
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• 제24권10호
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• pp.794-798
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• 2011

This paper was carried out design of 1,700 V Base Resistance Thyristor for fabrication. We decided conventional BRT (base resistance thyristor) device and Trench Gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 2,000 V breakdown voltage and 3.0 V Vce,sat. At the same time, we carried out field ring simulation for obtaining high voltage.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.789-792
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• 2007

이 연구는 Sentaurus Device를 이용하여 여러 가지 캐리어 전송 모델에 대한 반도체의 구조적, 전기적, 열적 작용의 변화를 조절함으로써 공정과 설계를 보다 쉽게 개발하는데 도움이 되리라 본다. 즉, 여러 가지 캐리어 전송 모델들은 밀도구배 모델을 기반으로 확산작용과 유체역학, Monto Carlo 전송 모델로 각기 분류할 수 있다. 각각의 모델들은 필수적인 요소에 의존하여 서로 다른 형태로 나타내어 질 수 있다. 이 연구에서는 Sentaurus Device simulation을 통하여 여러 가지 형태의 캐리어 전송 모델의 변화를 시각적으로 관찰할 것이다.

• Smart Structures and Systems
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• 제26권5호
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• pp.605-617
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• 2020

In this study, the experimental tests for the direct tensile strength measurement of Ultra-High Performance Concrete (UHPC) were numerically modeled by using the discrete element method (circle type element) and Finite Element Method (FEM). The experimental tests used for the laboratory tensile strength measurement is the Compressive-to-Tensile Load Conversion (CTLC) device. In this paper, the failure process including the cracks initiation, propagation and coalescence studied and then the direct tensile strength of the UHPC specimens measured by the novel apparatus i.e., CTLC device. For this purpose, the UHPC member (each containing a central hole) prepared, and situated in the CTLC device which in turn placed in the universal testing machine. The direct tensile strength of the member is measured due to the direct tensile stress which is applied to this specimen by the CTLC device. This novel device transferring the applied compressive load to that of the tensile during the testing process. The UHPC beam specimen of size 150 × 60 × 190 mm and internal hole of 75 × 60 mm was used in this study. The rate of the applied compressive load to CTLC device through the universal testing machine was 0.02 MPa/s. The direct tensile strength of UHPC was found using a new formula based on the present analyses. The numerical simulation given in this study gives the tensile strength and failure behavior of the UHPC very close to those obtained experimentally by the CTLC device implemented in the universal testing machine. The percent variation between experimental results and numerical results was found as nearly 2%. PFC2D simulations of the direct tensile strength measuring specimen and ABAQUS simulation of the tested CTLC specimens both demonstrate the validity and capability of the proposed testing procedure for the direct tensile strength measurement of UHPC specimens.

• 전자공학회논문지A
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• 제33A권7호
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• pp.198-204
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• 1996

Electron beam lithography is one of the importnat technologies which can delineate deep submicron patterns. REcently, electron beam lithography is being applied in delineating the critical layers of semiconductor device fabrication. In this paper, we present a development simulation program for electron beam lithography and study the development profiles of resist when resist is exposed by the electron beam. Experimentally, the development parameter of positive and negative resists are measured and the data is applied to input parameter of the simulation program. Also simulation results are compared of the process results in the view of resist profiles. As a result, for PMMA and SAL 601 resist, the trend of simulation to the values of process parameters agree with real process results very well, so that the process results can be predicted by the simulation.