• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.6
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• pp.387-396
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• 2014

Recently, there have been continuous efforts and progresses regarding the research on diverse network control and management platforms for SDN (Software Defined Networking). SDN is defined as a new technology to enable service providers/network operators easily to control and manage their networks by writing a simple application program. In SDN, incomplete or malicious programmable entities could cause break-down of underlying networks shared by heterogeneous devices and stake-holders. In this sense, any misunderstanding or diverse interpretations should be completely avoided. This paper proposes a new framework for SDN application verification and a prototype based on the formal method, especially with process algebra called pACSR which is an extended version of Algebra of Communicating Shared Resources (ACSR).

• Journal of Service Research and Studies
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• v.8 no.1
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• pp.59-72
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• 2018

In the perspective of service, it is important to institute certification process required by International Standard Organization (ISO) for software (SW) development process, since Information and Communication Technology (ICT) takes high portion of the Korean industry and its certification for SW is essential internationally for trade. In addition, the certification service provided by BPMN tools like ADONIS is absolutely necessary. In that perspective, this paper proposes a new approach to satisfy this kind of necessity. This approach provides the certification service for the safety of SW required at the international level in Korean industry. Furthermore, the approach can be applied to other domains beside the SW. In order to demonstrate the approach, this paper shows how to guarantee service design for certification of ECSS-E-40 of European Space Agency (ESA) with ADONIS. This paper focuses on specification and verification of SW in E-40, and the main requirement for the verification will be safety of the SW.

• Journal of the Korea Society for Simulation
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• v.27 no.3
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• pp.23-36
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• 2018

Discrete Event System Specification (DEVS) has been used for decades as it provides sound semantics for hierarchical modular specification of discrete event systems. Instead of the mathematical specification, the DEVS diagram, based on the structured DEVS formalism, has provided more intuitive and convenient representation of complex DEVS models. This paper proposes a clean room process for implementation and verification of a DEVS diagram model specification into a simulation software source code. Specifically, it underlies a sequence of transformation steps from conformance and integrity checking of a given diagram model, translation into a corresponding tabular model, and finally conversion to a simulation source code, with each step being inversely verifiable for traceability. A simple example helps developers to understand the proposed process with associated transformation methods; a case study shows that the proposed process is effective for and adaptable to practical simulation software development.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.18 no.9
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• pp.72-80
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• 2019

In this task, the tool dynamometer design and manufacture, and the Ansys S/W structural analysis program for tool attachment that satisfies the cutting force measurement requirements of the tool dynamometer system are used to determine the cutting force generated by metal cutting using 3-axis static structural analysis and the LabVIEW system. The cutting power in a cutting process using a milling tool for processing metals provides useful information for understanding the processing, optimization, tool status monitoring, and tool design. Thus, various methods of measuring cutting power have been proposed. The device consists of a strain-gauge-based sensor fitted to a new design force sensing element, which is then placed in a force reduction. The force-sensing element is designed as a symmetrical cross beam with four arms of a rectangular parallel line. Furthermore, data duplication is eliminated by the appropriate setting the strain gauge attachment position and the construction of a suitable Wheatstone full-bridge circuit. This device is intended for use with rotating spindles such as milling tools. Verification and machining tests were performed to determine the static and dynamic characteristics of the tool dynamometer. The verification tests were performed by analyzing the difference between strain data measured by weight and that derived by theoretical calculations. Processing test was performed by attaching a tool dynamometer to the MCT to analyze data generated by the measuring equipment during machining. To maintain high productivity and precision, the system monitors and suppresses process disturbances such as chatter vibration, imbalances, overload, collision, forced vibration due to tool failure, and excessive tool wear; additionally, a tool dynamometer with a high signal-to-noise ratio is provided.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.11a
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• pp.397-398
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• 2007

• Journal of IKEEE
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• v.15 no.4
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• pp.267-273
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• 2011

In hardware design, its stability and reliability are important, because a hardware error can cause serious damages or disaster. To improve stability and reliability, this paper presents the implementation of the hardware verification system using the fault injection method in PC environment. This paper presents a verification platform that can verify hardware system reliably and effectively, through a process to generate faults as well as insert input signals into the actual running system environment. The verification system is configured to connect a PC with a digital I/O card, and it can transmit or receive signals from the target system, as a verifier's intention. In addition, it can generate faults and inject them into the target system. And it can be monitored by displaying the received signals from the target system to the graphical wave signals. We can evaluate its reliability by analyzing the graphical wave signals. In this paper, the proposed verification system has been applied to the FPGA firmware of a nuclear power plant control system. As a result, we found its usefulness and reliability.

• Journal of the Korea Society of Computer and Information
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• v.27 no.12
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• pp.209-217
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• 2022

Naval CMS(Combat Management System) is linked to various sensors and weapon equipment and use DDS(Data Distribution Service) for efficient data communication between ICU(Interface Control Unit) Node and IPN(Information Processing Node). In order to use DDS, software in the system communicates in an PUB/SUB(Publication/Subscribe) based on DDS topic. If the DDS messages structure in this PUB/SUB method does not match, problems such as incorrect command processing and wrong information delivery occur in sending and receiving application software. To improve this, this paper proposes a DDS message structure integrity verification method. To improve this, this paper proposes a DDS message structure integrity verification method using a hash tree. To verify the applicability of the proposed method to Naval CMS, the message integrity verification rate of the proposed method was measured, and the integrity verification method was applied to CMS and the initialization time of the existing combat management system was compared and the hash tree generation time of the message structures was measured to understand the effect on the operation and development process of CMS. Through this test, It was confirmed that the message structure verification method for system stability proposed in this paper can be applied to the Naval CMS.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2289-2298
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• 1997

This paper proposes a new method to recognize map. In order to minimize the ripple effect of one recognition result affecting another, the structural information is represented with a hierarchical model. and the model is used in both the recognition and verification process. Furthermore, lines related to an entity are searched in a used in both the recognition and verification process. Furthermore, lines related to an entity are searched in a reduced search space by defining some relations between lines. When there is a mis-recognition after verificaiton, recognition process will be retired. In the process, the accurate result can obtained through the change of the parameter values used in the algorithm. As a result, the search space is reduced effectively, and even objects that embodies the broken lines and the crossed lines are recognized.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.8
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• pp.150-156
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• 2001

This paper deals with the theoretical estimation and its experimental verification of grinding wheel wear in surface grinding process. A theoretical formulation is provided to predict the grinding wheel wear in surface grinding. To validate the theoretical prediction, the grinding wheel wear is measured by using a laser scanning micrometer. The associated surface roughness and grinding farce are also investigated both theoretically and experimentally. Through a series of simulations and experiments, it is shown that the predictions are in good agreement with the experimental results.