• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.82-88
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• 2015

This paper presents a design of the enable switch circuit, which is consist of discrete device at smart junction box(SJB) board. The Enable switch circuit, which receives ignition signal (IG) for input, sends a drive signal to linear regulator and other elements. The circuit design is carried out in a BCDMOS $0.18{\mu}m$ technology, and the performances are verified through simulations according to AEC-Q100 and ISO 7637-2. Die area of the designed Enable switch circuit is $1.67mm{\times}0.54mm$ in layout, and it is shown that the die can be housed in $3mm{\times}3mm$ HVSON8 package. The designed enable switch circuit is expected to be widely adopted in various automotive SJB's since it can significantly reduce the overall printed circuit board form factor.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.1
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• pp.111-116
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• 2001

A practical scheme to reduce failure of the PCB(Printed Circuit Board) of a monitor is introduced using deformed mode shape under mechanical shock. When the monitor is given critical shock loads, cracks are commonly initiated at the tip of a hole on the PCB. Accordingly, a deformed mode shape of the PCB is obtained using a FEM code to define a weak point on the PCB under mechanical shock, and then the position and direction of the hole is determined to prevent the failure at the critical mode shape. Also, the stress intensity factor around the weak point on the PCB is calculated to check the possibility of fracture by normal tensile stress. In conclusion, present research is useful to assist the practical design of components-layout on the PCB.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.753-759
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• 2014

This paper introduces the reduction design technique of the resonance phenomenon of the inner PCB based on power integrity from the analysis about the inner power supply line generating RLC resonance. With the technique, the resonant frequency resulted from the structural characteristics of the PCB can be analyzed and allows to predict and the capacitor for resonance phenomenon reduction can be decided as a decoupling capacitor. From the simulation result, it was confirmed that the PCB's resonance phenomenon reduction design technique should have the reduction effect in the inner motherboard of the industrial controller. This research will be contributed to the improvement of the safety of a PDN (Power Delivery Network) structure in the layout design technique of the PCB.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.7
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• pp.310-316
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• 2019

In automotive application, customers are demanding high efficiency and various functions for convenience. The demand for these automotive applications is steadily increasing. In this study, it has been studied the analysis of heat flow to improve the PCB(printed circuit board) heating performance of WPC (wireless power charger) recently developed for convenience. The charging performance of the wireless charger has been reduced due to power dissipation and thermal resistance of PCB. Therefore, it has been proposed optimal PCB design, layout and position of electronic parts through the simulation of heat flow analysis and PCB design was analyzed and decided at each design stage. Then, the experimental test is performed to verify the consistency of the analysis results under actual environmental conditions. In this paper, The PCB modeling and heat flow simulation in transient response were performed using HyperLynx Thermal and FloTHERM. In addition, the measurement was performed using infrared thermal imaging camera and used to verify the analysis results. In the final comparison, the error between analysis and experiment was found to be less than 10 % and the heating performance of PCB was also improved.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.280-288
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• 2016

Microelectronic product consumers may already be expecting another paradigm shift with smarter phones over smart phones, but the current status of microelectronic manufacturing engineering education (MMEE) in universities hardly makes up the pace for such a fast moving technology paradigm shift. The purpose of MMEE is to educate four-year university graduates to work in the microelectronics industry with up-to-date knowledge and self-motivation. In this paper, we present a comprehensive curriculum for a four-year university degree program in the area of microelectronics manufacturing. Three hands-on experienced-based courses are proposed, along with a methodology for undergraduate students to acquire hands-on experience, towards integrated circuits (ICs) design, fabrication and packaging, are presented in consideration of manufacturing engineering education. Semiconductor device and circuit design course for junior level is designed to cover how designed circuits progress to micro-fabrication by practicing full customization of the layout of digital circuits. Hands-on experienced-based semiconductor fabrication courses are composed to enhance students’ motivation to participate in self-motivated semiconductor fab activities by performing a series of collaborations. Finally, the Microelectronics Packaging course provides greater possibilities of mastered skillsets in the area of microelectronics manufacturing with the fabrication of printed circuit boards (PCBs) and board level assembly for microprocessor applications. The evaluation of the presented comprehensive curriculum was performed with a students’ survey. All the students responded with “Strongly Agree” or “Agree” for the manufacturing related courses. Through the development and application of the presented curriculum for the past six years, we are convinced that students’ confidence in obtaining their desired jobs or choosing higher degrees in the area of microelectronics manufacturing was increased. We confirmed that the hypothesis on the inclusion of handson experience-based courses for MMEE is beneficial to enhancing the motivation for learning.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.