• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.134-139
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• 2006

In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1081-1084
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• 1998

In this paper, we propose the bus coding technique for low power consumption. For CMOS circuit most power is dissipated as dynamic power for charging and discharging node capacitances.Though the I/O and bus are likely to have the very large capacitances associated with them and dissipate much of the power dissipated by an IC, they have little beenthe special target for power reduction. The conventional Bus-Invert coding method can't decrease the peak power dissipation by 50% because the additional invert signal line can invoke a transition at the time when Bus-Invert coding isn't used to code original bus data. The proposed technique always constraints the Hamming distance between data transferred sequentially to be below the half of the bus width, and thus decrease the I/O peak power dissipation and the I/O average power dissipation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.11
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• pp.2007-2016
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• 2011

In this paper, a new algorithm for alleviating overloads in power networks by the use of line power tracing and sensitivity is proposed to perform line switching and bus separation effectively. Also, a new bus separation index based on line power tracing is presented to find the bus to be separated for relieving overloads effectively. By applying the sensitivity of the line flow with respect to the change of the line impedance, both switching-on and switching-off of the lines for alleviating overloads in power networks are performed systematically at once. The number of the considered cases for line switching and bus separation can be greatly reduced and the best combination of line switching and bus separation can be acquired efficiently by the use of the sensitivity and the bus separation index. In order to show the effects of this algorithm, it is applied to a small scale power system of IEEE 39-bus system and practical power systems of KEPCO.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.201-205
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• 2001

This paper presents the load modeling process and bus load models for KEPCO power system. At first, load devices commonly used in KEPCO power systems were selected, and tested for measuring the voltage and frequency sensitivity of active and reactive power. From this test, about 40 voltage and frequency dependent load models have been obtained. The bus load composition rate for KEPCO power system has been determined using the various recent surveys and papers in order to develop the load model for a power system bus. To verify the accuracy of developed bus load models, the field test for measuring active and reactive power according to artificial variation of the bus voltage was performed at 8 substations for spring summer, autumn, winter cases. With data of this seasonal field test, more reliable bus load models for KEPCO power systems were developed.

• Journal of Power Electronics
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• v.9 no.3
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• pp.447-455
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• 2009

The power supply systems, which require low-voltage / high-current output has been changing from the conventional centralized power system to a distributed power system. The distributed power system consists of a bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of a bus converter input impedance of POL causes system instability and has been an actual problem. By increasing the bus capacitor, the system stability can be easily improved. However, due to limited space on the system board, the increasing of bus capacitors is impractical. An urgent solution of this issue is strongly desired. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of a bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed and then conformed experimentally for stability criterion. Furthermore, the design process of each control schemes for system stability is proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.662_663
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• 2009

Motor bus transfer involves the process of transferring a bus that has several critical motors to an alternate source of power when the main normal power source feeding them is interrupted. Bus transfer is a time-critical application in which the transfer progress depends on various parameters such as the type of motor, load on the motor at the time of transfer, inertia of the motor, and the combined open-circuit time constant of various motors present on the bus at the time of transfer. This paper present the result of modeling and simulation of nuclear power motor bus using ETAP(Electrical Transient Analyzing Program) program for motor and motor bus residual voltage decay characteristics.

• Journal of information and communication convergence engineering
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• v.15 no.4
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• pp.237-243
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• 2017

This paper presents an analysis of the electromagnetic interference of a heterogeneous power bus where electromagnetic bandgap (EBG) cells are irregularly arranged. To mitigate electrical-noise coupling between high-speed circuits, the EBG structure is placed between parallel plate waveguide (PPW)-based power buses on which the noise source and victim circuits are mounted. We examine a noise suppression characteristic of the heterogeneous power bus in terms of scattering parameters. The characteristics of the dispersion and scattering parameters are compared in the sensitivity analysis of the EBG structure. Electric field distributions at significant frequencies are thoroughly examined using electromagnetic simulation based on a finite element method (FEM). The noise suppression characteristics of the heterogeneous power bus are demonstrated experimentally. The heterogeneous power bus achieves significant reduction of electrical-noise coupling compared to the homogeneous power buses that are adopted in conventional high-speed circuit design. In addition, the measurements show good agreement with the FEM simulation results.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.85-89
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• 2004

This paper presents Power Control and Distribution Unit development of GEO satellite with 3kW power output. The sensing error of bus voltage produce control signal of the shunt switch assembly and battery power converter, and the tolerance of error signals generated decide the stability of proposed system. The dynamic characteristics of main bus according to the load changing and the control logic of FPGA are simulated. In order to verify the proposed design, the simulation and experimental results for solar array shunt switch, battery power converter and bus controller are shown.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1617-1624
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• 2012

A DC power system has many loads with varied functions. Also, there may be large pulsed loads with short duty ratios which can affect the normal operation of other loads. In this paper, Voltage Bus Conditioner(VBC) without any current sensors is proposed to damp the bus voltage transients by parallel pulsed loads. The proposed control approach requires only one voltage sensor and carries out both the functions of damping the bus voltage transients and maintaining the level of energy stored. The proposed control technique has been implemented on a TMS320F2812 Digital Signal Processor(DSP). Simulated results by a Matlab Simulink and experimental results are presented which verify the control principles and demonstrate the practicalty of the approach.