• 한국태양에너지학회:학술대회논문집
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• 2008.04a
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• pp.43-48
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• 2008

Through simulations and field experiment on A.C. parallel operation of both Utility Interactive Photovoltaic System and Diesel Engine Revolving Field Type Synchronous Generator, following factors have been found. First, the inverter should be operated in three modes of frequency(mode.1: ${\pm}$0.3Hz, mode.2: ${\pm}$1Hz, mode.3: ${\pm}$2Hz) as default, considering properties of operating Synchronous Generator. Second, as a result of supplying 13.5kW of residual power, it has been found that Synchronous Generator takes the power input only as reactive power, because it was electrically stable with frequency of 60.14Hz and high voltage of 222.3V even when power factor was -0.94. Besides, it was mechanically stable, too, because the quake, noise, and temperature of Synchronous Generator in this case were 7.5mm/s, 97dB, and $6^{\circ}C$ respectively, which were lower than normal load connection of 145.6kW; 11.03mm/s. Thus, load share of Revolving Field Type Synchronous Generator reduces according to the supply of Photovoltaic System to the load power. In this experiment, 200kW of Synchronous Generator and 40kW of Photovoltaic System were operated in parallel. The load share was 20% in maximum. and 11.1lit/hr of fuel was saved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.87-93
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• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.77-84
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• 2007

In this parer, a wideband low-noise amplifier (LNA) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion RF receivers. By exploiting the inverter-type transimpedance input stage with a 3rd-order Chebyshev matching network, the wideband LNA demonstrates the measured results of the -3dB bandwidth of 5.35GHz, the power gain (S21) of $12\sim18dB$, the noise figure (NF) of $6.9\sim10.8dB$, and the broadband input/output impedance matching of less than -10dB/-24dB within the bandwidth, respectively. The chip dissipates 32.4mW from a single 1.8V supply, and occupies the area of $0.56\times1.0mm^2$.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.53-60
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• 2010

This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.100-105
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• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.43-50
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• 2016

In this paper, new automatic LC calibrator is proposed for realizing a passive LC filter with almost constant frequency characteristic regardless of the PVT variations. The SAW-less GPS RX front-end is implemented using a 65nm CMOS process using the proposed LC calibrator. Also, new dual-mode low noise amplifier (LNA) structure is proposed to generate the RF signal required for the LC calibrator. The characteristics of the implemented GPS RX front-end show the voltage gain of about 42.5 dB, noise figure of below 1.35 dB, the blocker input P1dB of -24 dBm in case of the worst blocker signal at 1710 MHz frequency, while it consumes 7 mA current at 1.2 V power supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2369-2379
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• 2013

A CMOS x-ray line scan sensor which is used in both medical imaging and non-destructive diagnosis is designed. It has a pixel array of 512 columns ${\times}$ 4 rows and a built-in DC-DC converter. The pixel circuit is newly proposed to have three binning modes such as no binning, $2{\times}2$ binning, and $4{\times}4$ binning in order to select one of pixel sizes of $100{\mu}m$, $200{\mu}m$, and $400{\mu}m$. It is designed to output a fully differential image signal which is insensitive to power supply and input common mode noises. The layout size of the designed line scan sensor with a $0.18{\mu}m$ x-ray CMOS image sensor process is $51,304{\mu}m{\times}5,945{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.7-14
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• 2008

In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.84-89
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• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop dual split ring resonator is presented for reducing the phase noise. The square-shaped dual split ring resonator having the form of the microstrip square open loop is investigated to reduce the phase noise. Compared with the microstrip square open loop resonator and the microstrip square open loop split ring resonator as well as the conventional microstrip line resonator, the microstrip square dual split ring resonator has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power supply has the phase noise of -123.2~-122.0 dBc/Hz @ 100 kHz in the tuning range, 11.74~11.75 GHz. The figure of merit (FOM) of this VCO is-214.8~-221.7 dBc/Hz dBc/Hz @ 100 kHz in the same tuning range. Compared with VCO using the conventional microstrip line resonator, VCO using microstrip square open loop resonator, the phase noise of VCO using the proposed resonator has been improved in 26 dB, 10 dB, respectively.