• 전자공학회논문지C
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• 제34C권6호
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• 전자공학회논문지C
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• 제34C권12호
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• 전력전자학회논문지
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• 제9권5호
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• pp.507-515
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• 2004

고속 스위칭 소자의 출현과 함께 높은 전압 상승률(dv/dt)은 PWM 인버터에 EMI 노이즈 및 축 전압 그리고 베어링 누설전류 등의 문제 등을 발생시키고 있다. 본 논문에서는 유도전동기 시스템에서의 새롭게 개발된 전도성 EMI 저감 SVPWM 기법의 응용에 대하여 기술한다. 새롭게 개발된 커먼모드 전압제거 SVPWM 기법은 인버터 제어에 있어서 영벡터 상태를 사용하지 않고 종래의 PWM 기법에 비하여 커먼모드 전압의 감소가 가능하다. 소프트웨어 접근에 의한 제안된 기법의 타당성은 시뮬레이션과 실험적 결과를 통하여 확인하였다.

• ETRI Journal
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• 제44권3호
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• pp.379-388
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• 2022

This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

• 한국전자통신학회논문지
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• 제9권7호
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• pp.753-759
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• 2014

본 논문에서는 전원무결성(Power Source Integrity) 해석을 기반으로 PCB(Printed Circuit Board)내부 전원 선로의 RLC 공진(Resonance)현상을 해석하고 PCB내부 공진현상 감쇄를 위한 설계기법을 제시한다. 제시하는 기법은 PCB의 구조적 특성으로 형성되는 공진주파수를 예측하며, 공진현상 감쇄를 위한 디커플링 캐패시터의 적용위치 및 용량을 결정할 수 있다. 본 논문에서는 산업용 제어기 내부의 메인보드 회로 시뮬레이션 모델을 통해서 PCB 공진현상 감쇄 설계기법에 대한 타당성을 검증하였다. 본 연구결과는 향후, PCB 회로 설계에서 PDN(Power Delivery Network)구조의 안정도 향상에 기여할 것으로 기대된다.

• Journal of electromagnetic engineering and science
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• 제8권3호
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• pp.119-128
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• 2008

In this paper, we propose a developing approach of 600 W super high frequency(SHF) traveling wave tube amplifier (TWTA) for communications. Also, we make a TWTA called the experimental-TWTA(ETWTA), which uses a cathode ripple reduction technique to improve RF performance. After implementation, we discuss, and compare it with some other TWTAs. Its RF performance is better than that of other TWTAs. Therefore, this methodology can be used to develop the high power SHF TWTA for communications.

• Journal of Magnetics
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• 제21권4호
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• pp.593-598
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• 2016

In order to reduce the amount of noise component in X-ray imaging system, various reduction techniques were frequently used in the field of diagnostic imaging. Although the previous techniques -such as median, Wiener filters and Anscombe noise reduction technique - were able to reduce the noise, the edge information was still damaged. In order to cope with this problem, total variation (TV) noise reduction technique has been developed and researched. The purpose of this study was to evaluate and compare the image quality using normalized noise power spectrum (NNPS) and contrast-to-noise ratio (CNR) through simulations and experiments with respect to the above-mentioned noise reduction techniques. As a result, not only lowest NNPS value but also highest CNR values were acquired using a TV noise reduction technique. In conclusion, the results demonstrated that TV noise reduction technique is proved as the most practical method to ensure accurate denoising in X-ray imaging system.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권7호
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.531-534
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• 2005

This paper presents a new data line sharing technique for TFT-LCD panels. This technique reduces the number of data driver IC's to half by having two adjacent pixels share the same data line. This in turn doubles the number of gate lines, which are integrated directly on the glass substrate of amorphous silicon for further cost reduction and more compactness. The proposed technique with new pixel array structure was applied to 15.4 inch WXGA TFT-LCD panels and has proven that the number of driver IC's were halved with nearly 41% circuit cost reduction and 5.3% reduction in power consumption without degrading the image quality.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.321-324
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• 2005

This paper describes the application of newly developed conducted EMI reduction technique of SVPWM in induction motor drive. The newly developed common mode voltage reduction SVPWM technique doesn't any zero-voltage vector states for inverter control. Hence it can restrict the common mode voltage better than conventional PWM technique. The proposed technique is verified through simulation and experimental results. And by applying vector-controled system, the proposed technique have superior ability of reducing EMI and equal control performance comparing conventional SVPWM technique.