• The Journal of Engineering Geology
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• v.23 no.1
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• pp.29-36
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• 2013

The application of appropriate rehabilitation methods can improve the efficiency of clogged wells and extend their life. In this paper, we study the feasibility of well cleaning using high-voltage pulsed discharge, in which electrical energy is used to produce impulsive pressure in water, in contrast to conventional methods that employ chemical or pneumatic energy sources. This technique utilizes the compressive shock wave generated by the expansive force of hot, dense plasma that is produced during a pulsed discharge in the gap between electrodes immersed in water. Compared with conventional techniques, this method is simple, and easy to handle and control. Using a capacitive pulsed power system with an electrical energy of 200 J, an impulsive pressure of 10.7 MPa is achieved at the position 6 cm away from the discharge gap. The amplitude of the impulsive pressure was easily controlled by adjusting the charging voltage of the capacitor and was almost linearly proportional to peak discharge current. The technique achieved good results in cleaning feasibility tests with mock-up specimens similar to clogged well screens.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1104-1112
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• 2013

This paper presents a wideband Colpitts voltage controlled oscillator(VCO) with nanosecond startup time and a center frequency of 8.35 GHz for a new bubble-type motion detector that has a bubble-layer detection zone at the specific distance from itself. The VCO circuit consists of two parts; one is a negative resistance part with a HEMT device and Colpitts feedback structure and the other is a resonator part with a varactor diode and shorted shunt microstrip line. The shorted shunt microstrip line and series capacitor are utilized to compensate for the input reactance of the packaged HEMT that changes from capacitive values to inductive values at 8.1 GHz due to parasitic package inductance. By tuning the feedback capacitors which determine negative resistance values, this paper also investigates startup time improvement with the negative resistance variation and tuning bandwidth improvement with the reactance slope variation of the negative resistance part. The VCO measurement shows the tuning bandwidth of 2.3 GHz(28 %), the output power of 4.1~7.5 dBm and the startup time of less than 2 nsec.

• Journal of the Korean Ceramic Society
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• v.49 no.5
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• pp.475-483
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• 2012

High capacitance X5R MLCCs based on $BaTiO_3$ ceramic dielectric layers exhibit a single broad, asymmetric arc shape impedance and modulus response over the wide frequency range between 1 MHz to 0.01 Hz. Analysis according to the conventional brick-layer model for polycrystalline conductors employing a series connection of multiple RC parallel circuits leads to parameters associated with large errors and of little physical significance. A new parametric impedance model is shown to satisfactorily describe the experimental spectra, which is a parallel network of one resistor R representing the DC conductivity thermally activated by 1.32 eV, one ideal capacitor C exactly representing bulk capacitance, and a constant phase element (CPE) Q with complex capacitance $A(i{\omega})^{{\alpha}-1}$ with ${\alpha}$ close to 2/3 and A thermally activated by 0.45 eV or ca. 1/3 of activation energy of DC conductivity. The feature strongly indicate the CK1 model by J. R. Macdonald, where the CPE with 2/3 power-law exponent represents the polarization effects originating from mobile charge carriers. The CPE term is suggested to be directly related to the trapping of the electronic charge carriers and indirectly related to the ionic defects responsible for the insulation resistance degradation.

• Journal of the Korean Electrochemical Society
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• v.20 no.2
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• pp.34-40
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• 2017

Electric double layer capacitors (EDLC: electric double layer capacitors) have drew attention as an energy storage device for the next generation because of their outstanding power capability and durability. But their usage is somewhat limited due to low energy density over secondary batteries. One of methods to improve the energy of EDLC is expanding the voltage window of cell operation by increasing the charge cut-off voltage. In this study, $SBP-BF_4$ (spirobipyrrolidinium tetrafluoroborate), $TEA-BF_4$ (tetraethylammonium tetraflouroborate) and $EMI-BF_4$ (1-ethyl-3-methylimidazolium tetrafluoroborate) in AN (acetonitrile) were selected to evaluate the possibility of application at high voltage environment. The LSV (linear sweep voltammetry) measurements showed that the 1.5M SBP-BF4/AN electrolyte was stable over a wide potential window and showed the best electrochemical performance compared to other combinations of electrolytes at high voltage environments (over 3.0 V). Furthermore, TMSP (tris(trimethylsilyl) phosphite) was applied to 1.5M SBP-BF4/AN in order to maintain stable performance at high voltage for the long period of time. The electrolyte with TMSP additive showed the capacity retention of 93% after 10,000 cycles at 3.3 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.89-96
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• 2015

This paper presents a high efficiency, PSM/DCM/CCM triple mode boost DC-DC converter for mobile application. This device operates at Pulse-Skipping Mode(PSM) when it enters light load, and otherwise operate the operating frequency of 1.4MHz with Pulse-Width Modulation(PWM) mode. Especially in order to improve the efficiency during the Discontinuous-Conduction Mode(DCM) operation period, the reverse current prevention circuit and oscillations caused by the inductor and the parasitic capacitor to prevent the Ringing killer circuit is added. The input voltage of the boost converter ranges from 2.5V ~ 4.2V and it generates the output of 4.8V. The measurement results show that the boost converter provides a peak efficiency of 92% on CCM and 87% on DCM. And an efficiency-improving PWM operation raises the efficiency drop because of transition from PWM to PFM. The converter has been fabricated with a 0.18um Dongbu BCDMOS technology.

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.48-53
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• 2002

Ferroelectric $Pb_{0.99}[(Zr_{0.6}Sn_{0.4})_{1-x}Ti_x]_{0.98}Nb_{0.02}O_3$(PNZST) thin films were deposited by a RF magnetron sputtering on $(La_{0.5}Sr_{0.5})CoO_3$(LSCO)/Pt/Ti/$SiO_2$/Si substrate using a PNZST target with excess PbO of 10 mole%. The crystallinity and electrical properties of the thin films with various composition ratio were investigated. The thin films deposited at the substrate temperature of $500^{\circ}C$ and the power of 80 W were crystallized to a perovskite phase after rapid thermal annealing(RTA) at $650^{\circ}C$ for 10 seconds in air. A PNZST thin films with Ti of 10 mole% showed the good crystallinity and ferroelectric properties. The remanent polarization and coercive field of the PNZST capacitor were about $20\;{\mu}C/cm^2$ and 50 kV/cm, respectively. The reduction of the polarization after $2.2{\times}10^9$ switching cycles was less than 10%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.473-478
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• 2001

Ferroelectric P $b_{0.99}$［(Z $r_{0}$ 6S $n_{0.4}$)/0.9/ $Ti_{0.1}$］0.98/N $b_{0.02}$ $O_3$(PNZST) thin films were deposited by a RF magnetron sputtering on L $a_{0.5}$S $r_{0.5}$Co $O_3$(LSCO)/Pt/Ti/ $SiO_2$/Si substrate using a PNZST target with excess PbO of 10 mole%. The crystallinity and electrical properties of the thin films annealed at various temperature and time were investigated. The thin films deposited at the substrate temperature of 500 $^{\circ}C$ and the power of 80 W were crystallized to a perovskite phase after rapid thermal annealing(RTA). The thin films annealed at 650 $^{\circ}C$ for 10 seconds in air exhibited the good crystal structures. The remanent polarization and coercive field of the PNZST capacitor were about 20 $\mu$C/$\textrm{cm}^2$ and 50 kV/cm, respectively. The reduction of the polarization after 2.2$\times$10$^{9}$ switching cycles was less than 10 %..10 %......

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.