• 전기전자학회논문지
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• 제23권1호
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• pp.326-329
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• 2019

차세대 전력반도체 소재인 질화갈륨(GaN)이 증착된 GaN-on-Si 기판의 기술성숙도가 높아지면서 Si CMOS 소자와의 단일기판 집적화에 대한 관심이 고조되고 있다. CMOS 특성이 상대적으로 저하되는 (111)Si 보다 (110)Si의 CMOS소자가 집적화 관점에서 유리할 것으로 판단되며, 따라서 향후 전개될 GaN-on-(110)Si 플랫폼을 활용한 GaN 전력반도체 스위치소자와 Si CMOS소자의 단일기판 집적화에 적용될 수 있도록 국내 Si CMOS 파운드리 공정을 (110)Si 기판에 진행하였다. 제작된 CMOS소자의 기본특성 및 인버터체인 회로특성, 그리고 게이트 산화막의 신뢰성 분석을 통해 향후 국내 파운드리공정을 활용한 (110)Si CMOS기술과 GaN의 집적화의 가능성을 검증하였다.

• 에너지공학
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• 제22권1호
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• pp.58-81
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• 2013

탄화규소(SiC)나 질화갈륨(GaN)과 와이드갭 반도체를 이용한 전력소자의 생산기술이 크게 발전하여 그간 널리 사용되어 온 실리콘(Si) 전력소자와 비교하여 작동전압, 스위칭 속도 및 on-저항 등이 크게 향상되어 몇 개 기업은 제품화를 시작하였다. 내압 등 기술적 과제 등을극복하여 산업화를 하고자하는 움직임을 소개하고 아울러 연구동향도 분석한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.249-250
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• 2015

Technological advance of power elcetronic devices using semiconductor switches in last several decades, invoke the increase of switching devices' penetration in the system like STATCOM or HVDC and also, increase the difficulty to adjust switching characteristics in the virtual simulating configuration, which are not capable of reflect the detailed phenomena. To investigate harmful effect of switching devices into the grid, detailed modeling of power electronic devices are necessary, and the first step for entire grid modelling is simulate power system in time domain model. In this paper, simple two bus system with synchronous generator and infinite bus on the other side has been compromised in two simulation environment, using PSS/E and Matlab/Simulink. Comparing the result of two simulation result will give answers to the fundamental difference between two type of simulation environment.

• 한국전기전자재료학회논문지
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• 제26권3호
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• pp.190-193
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• 2013

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.95-98
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• 2003

Power semiconductors are being currently used as a application of intelligent power inverters to a refrigerator, a washing machine and a vacuum cleaner as well as core parts of industrial system. The rating of semiconductor devices is an important factor in decision on the field of application and the forward blocking voltage is one of factors in decision of the rating. The Power MOS device has a merit of high input impedance, short switching time, and stability in temperature as well known. Power MOS devices are mainly used as switches in the field of power electronics, especially the on-state resistance and breakdown voltage are regarded as the most important parameters. Power MOS devices that enable a small size, a light weight, high-integration and relatively high voltage are required these days. In this paper, we proposed the new lateral power MOS which has forward blocking voltage of 250V and contains trench electrodes and verified manufactural possibility by using TSUPREM-4 that is process simulator.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.330-333
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• 2002

The design of high power electronic circuits and the verification of the design by practical experiments are time and cost consuming. Recently power circuit simulation technique is developing to do it easily. However, most of the simulation has used the ideal switch model consists of passive component that can not describe the physical characteristics of semiconductor devices and cannot describe the switching transient state. For the design of such power electronic circuits by the simulation, the switching transients are very important. Therefore the simulation models must describe the switching transient and the stationary behavior as precisely as possible on the hand and as fast as possible the other hand. This paper introduces the application of the physical models of power devices that are developed by TUM(Technical University of Munich, Germany) for the power electronic circuit analysis.

• 전자통신동향분석
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• 제35권2호
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 C
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• pp.1559-1561
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• 2003

In northeast Asia, there will be several important HVDC transmission lines to be established in Korea and China for perspective electric network market. 5500V 4-inches High voltage thyristor can be used in the DC transmission and distribution of electric power system. In this application, many thyristors are connected in series for each thyristor valves. Therefore, the required low reverse-recovery charge QRR and low on-state voltage drop $V_{TM}$ for such thyristor is necessary to this application. In our work, the on-state and off-state voltage performance was simulated by commercial simulation software.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.213-217
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• 2015

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.

• 방사선산업학회지
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• 제2권3호
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• pp.141-148
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• 2008

Beta rays emitted from tritium in titanium tritide film were simulated with cathode rays of a scanning electron microscope to investigate the effect of beta rays from tritium on semiconductor devices. The cathode ray currents, which vary with the change of applied energy and beam spot size, were measured with Faraday cup. The current from the semiconductor device irradiated with cathode rays at various conditions was measured. The cathode ray current increased with the increase of spot size to a maximum then decreased when the spot sized increased further. The magnitude of current produced in the semiconductor device is proportional to the magnitude of cathode ray current. The magnitude of cathode ray current at each energy level was matched to the intensity of beta ray to simulate the tritium beta ray spectrum. Then the semiconductor characteristics were analyzed with I-V curves.