• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.252-255
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• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1356-1361
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• 2018

Replacing conventional Si diodes with SiC diodes in Si insulated gate bipolar transistor (IGBT) modules is advantageous as it can reduce power losses significantly. Also, the fast switching nature of the SiC diode will allow Si IGBTs to operate at their full high-switching-speed potential, which at present conventional Si diodes cannot do. In this work, the electrical test results for Si-IGBT/4HSiC-Schottky hybrid substrates (hybrid SiC substrates) are presented. These substrates are built for two voltage ratings, 1.7 kV and 3.3 kV. Comparisons of the 1.7 kV and the 3.3 kV Si-IGBT/Si-diode substrates (Si substrates) at room temperature ($20^{\circ}C$, RT) and high temperature ($H125^{\circ}C$, HT) have shown that the switching losses in hybrid SiC substrates are miniscule as compared to those in Si substrates but necessary steps are required to mitigate the ringing observed in the current waveforms. Also, the effect of design variations on the electrical performance of 1.7 kV, 50 A diodes is reported here. These variations are made in the active and termination regions of the device.

• 반도체디스플레이기술학회지
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• 제22권2호
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• pp.17-23
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• 2023

In semiconductor manufacturing processes, a cleaning process is important that can remove sub-micron particles. Conventional wet cleaning methods using chemical have limits in removing nano-particles. Thus, physical forces of a mechanical vibration up to 1 MHz frequency, was tried to aid in detaching them from the substrates. In this article, we developed a 1 MHz quartz megasonic for a bare wafer cleaning using finite element analysis. At first, a 1 MHz megasonic prototype was manufactured. Using the results, a main product which can improve a particle removal performance, was analyzed and designed. The maximum impedance frequency was 992 kHz, which agreed well with the experimental value of 986 kHz (0.6% error). Acoustic pressure distributions were measured, and the result showed that maximum / average was 400.0~432.4%, and standard deviation / average was 46.4~47.3%. Finally, submicron particles were deposited and cleaned for the assessment of the system performance. As a result, the particle removal efficiency (PRE) was proved to be 92% with 11 W power. Reflecting these results, the developed product might be used in the semiconductor cleaning process.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2007년도 춘계학술대회 논문집
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• pp.15-20
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• 2007

In this paper we introduce the IP3003 which provides excellent Power Factor and Total Harmonic Distortion to the power system. It is developed by Interpion Semiconductor co. LTD. However, the efficiency of power factor correction system is very difficult to analyze mathematically. In this paper, we use the numerical simulation methods for analyzing PFC systems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 전문대학교육위원 P
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• pp.7-9
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• 1999

Power semiconductor macro modeled by SIMULINK such as diode, thyristor. Loads are modeled by SIMULINK and PSPICE through their algorithms. For proved these modeling accurate, simulation techniques which are generally used in the field of power electronics circuits are adapted in power electronics and systems.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.287-290
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• 1998

This paper presents PWM method which modulates two third period only during one cycle of power converter. This method is compared with the conventionl sinusoidal modulation method applying to the power converter with large capacity necessitating low switching frequency. The presented modulation method enables to reduce power semiconductor rating, minimize switching loss, and improve the current wave form.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1236-1239
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• 2009

Each LCD TFT panel requires a power supply IC on the panel board. The IC provides the power rails for the timing controller, source and gated driver IC and others. The industry trend moves towards higher integrated devices. The challenge for the panel manufacturer is the development and implementation of such an IC in cooperation with the semiconductor supplier. If not done carefully the solution will not reduce the overall solution cost or can't provide the expected performance and reliability. This paper discusses the key considerations to successfully develop and integrate a highly integrated LCD bias IC into the system.

• 한국화재소방학회:학술대회논문집
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• 한국화재소방학회 2008년도 추계학술논문발표회 논문집
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• pp.189-194
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• 2008

Augmentation of the high-technology industry semiconductor factories, to acquire productivity and competitive power, is an international tendency. This situation is demanding for the functional counteractions. This study is regarding egress distance pertaining to installation of direct stairs. First, analyze situations and danger characteristics of LCD Factories. Second, through investigations and analysis of both domestic and foreign Egress Distance Code, propose rational Egress Distance Code pertaining to installation of direct stairs.

• E2M - 전기 전자와 첨단 소재
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• 제15권9호
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• pp.10-14
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• 2002

Plasma processing plays a significant role in semiconductor devices technology. Development of new plasma systems, such as high-density plasma reactors, required development of plasma theory to understand a whole process mechanism and to be able to explain and to predict processing results. A most important task in this way is to establish interconnections between input process parameters (working gas, pressure flow rate input power density) and a various plasma subsystems (electron gas, volume and heterogeneous gas chemistry, transport), which are closely connected one with other. It will allow select optimal ways for processes optimizations.