• 한국정보전자통신기술학회논문지
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• 제14권4호
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• pp.275-283
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• 2021

본 연구에서는 저내압 반도체 공정으로 제작 가능한 교류 구동 LED 드라이버 IC를 설계하여, 그 성능들에 대한 시뮬레이션을 수행하였다. 교류 220V에서 직접 구동하기 위한 드라이버 IC를 제작하기 위하여 500V 이상의 항복전압을 만족하는 반도체 제조공정이 필요하다. 고내압 반도체 제조공정은 일반적인 저내압 반도체 공정보다 매우 높은 제조비용을 요구한다. 따라서 낮은 내압의 소자를 구현하는 반도체 공정기술로도 제작할 수 있도록 LED 드라이버 IC를 직렬로 설계하였다. 이는 입력전압이 고전압이라도 각 LED 블록마다 전압이 나누어 인가되는 것을 가능하게 한다. LED 조명회로는 220V에서 96%의 역률을 나타내고 있다. pnp 트랜지스터를 이용한 역률 개선 회로에서는 99.7%의 아주 높은 역률을 얻을 수 있으며, 입력전압의 변동과 관계없이 매우 안정된 동작을 보여주었다.

• 마이크로전자및패키징학회지
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• 제30권2호
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• pp.43-51
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• 2023

본 논문에서는 전기차 전력변환 시스템의 근간이 되는 전력반도체 소자의 발전 방향과 차세대 전력반도체 소자인 wide bandgap (WBG)의 특징에 관해 소개하고자 한다. 현재까지의 주류인 Si insulated gate bipolar transistor (IGBT)의 특징에 관해 소개하고, 제조사 별 Si IGBT 개발 방향에 대해 다루었다. 또한 대표적인 WBG 전력반도체 소자인 SiC metal-oxide-semiconductor field-effect transistor (MOSFET)이 가지는 특징을 고찰하여 종래의 Si IGBT 소자 대비 SiC MOSFET이 가지는 효용 및 필요성에 대해 서술하였다. 또한 현 시점에서의 GaN 전력반도체 소자가 가지는 한계 및 그로 인해 전기자동차용 전력변환모듈 용으로 사용하기에 이슈인 점을 서술하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.426-429
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• 1988

A simple design method of a single balanced MMIC mixer is described. It uses small signal S11 and capacitive load for the input matching circuit and the output loading circuit, respectively. It is found that the conversion gain of the FET mixer is independent of FET gate width. The fabricated mixer has 2.5 dB conversion gain at 9 GHz with 50 ohm IF load and 2 dBm local oscillator power.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.41-45
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• 2002

In modem manufacturing, new applations and technologies demand smaller, and functional devices to replace large systems. As miniaturization becomes a necessity, many companies are interested in small pumps for use in creating ultra-high vacuum, but past efforts to develop such systems have failed due to problems with vibration, stress, heat and power consumption. This paper shows analysis-based design techniques for high vacuum turbomolecular pump by finite element analysis.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.159-160
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• 2015

Recently, it is increased to use the portable device with small size. It is also increasing for demand of a small size adapter. To reduce the size of components, switching frequency has to be increased. But it causes higher switching loss and temperature of components. Especially, the temperature of adapter must be limited because adapter can be easily touched when portable device is being charged. To reduce temperature of adapter, high efficiency is essential. To solve this problem, this paper proposes design of resonance frequency optimization for LLC converter with high efficiency and low temperature of passive components.

• Journal of the Optical Society of Korea
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• 제17권2호
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• pp.117-129
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• 2013

We briefly review the recent progress in passively mode-locked fiber lasers (PMLFLs) based on semiconductor saturable absorber mirrors (SESAMs) and discuss the detailed characterization of a SESAM-based, passively mode-locked erbium-doped fiber (EDF) laser operating in the 1.5-${\mu}m$ spectral range for various configurations. A simple and compact design of the laser cavity enables the PMLFL to generate either femtosecond or wavelength-tunable picosecond pulses with high stability as the intra-cavity filtering method is altered. All the cavities investigated in our experiments present self-starting, continuous-wave mode-locking with no Q-switching instabilities. The excellent stability of the source eventually enables the wavelength-tunable PMLFL to be used as a master oscillator for a power-amplifier source based on a large-core EDF, generating picosecond pulses of >10-kW peak power and >100-nJ pulse energy.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.83-83
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• 2009

We studied about the effect of newly developed etchant for spacer etch process in gate patterning. With the 110nm CMOS technology, first, we changed the gate pattern size and investigated the variation of spacer etch profile according to the difference in gate length. Second, thickness of spacer nitride was changed and effect of etch ant on difference in nitride thickness was observed. In addition to these, spacer etch power was added as test item for variation of etch profile. We investigated the etch profiles with SEM and TEM analysis was used for plasma damage check. With these results we could check the process margins for gate patterning which could hold best performance and choose the condition for best spacer etch profile.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.500-510
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• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.191-194
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• 2000

A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권10호
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.