• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.04a
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• pp.236-238
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• 1997

A cellular power amplifier using an APCVD(Atmospheric Pressure Chemical Vapor Deposition)-grown SiGe base HBT of ETRI has been designed with a linear simulation CAD. The Si/SiGe HBT with an emitter area of 2$\times$8${\mu}{\textrm}{m}$$^2$typically has a cutoff frequency(f$_{T}$) of 7.0 GHz and a maximum oscillation frequency(f$_{max}$) of 16.1 GHz with a pad de-embedding A packaged power Si/SiGe HBT with an emitter area of 2$\times$8$\times$80${\mu}{\textrm}{m}$$^2$typically shows a f$_{T}$ of 4.7 GHz and a f$_{max}$ of 7.1 GHz at a collector current (Ic) of 115 mA. The power amplifier exhibits a Forward transmission coefficient(S21) of 13.5 dB, an input and an output reflection coefficients of -42 dB and -45 dB respectively. Up to now the III-V compound semiconductor devices hale dominated microwave applications, however a rapid progress in Si-based technology make the advent of the Si/SiGe HBT which is promising in low to even higher microwave range because of lower cost and relatively higher reproducibility of a Si-based process.ess.ess.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.222-232
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• 2000

The relationship between carrier electron concentration(n) and atmosphere oxygen partial pressure($P_{O_2}$ for pure ZnO calculated by the mass-action law, well-known as n ${\propto}P^{-1/m}_{O_2}$ where m = 4 or 6 for the single or the double ionization of the native donor defects due to its nonstoichiometry, respectively, is found in competition with the calculation result on the basis that the total defect concentration is the sum of those of unionized and ionized defects. Definitively, it is found inconsistent with the calculation result by employing the Fermi-Dirac(FD) statistics for their ionization processes. By application of the FD statistics law to the ionization while assuming the defect formation is still ruled by the mass-action law, the calculation results shows the concentration is proportional to $P^{-1/2}_{O_2}$ whenever they ionize singly and/or doubly. Conclusively we would like to propose the new theoretical relation n ${\propto}P^{-1/m}_{O_2}$ because the ionization processes of donors in ZnO should be treated with the electronoccupation probability at localized quantum states in its forbidden band created by the donor defects, i.e. the FD statistics

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.249-251
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• 2003

This paper discribes the analysis of the breakdown voltage characteristics of SOI LIGBT with dual epi-layer. In case of SOI LIGBT with dual epi-layer, if we used high doping concentration in epi-layer, we obtained higher breakdown voltage compared with typical device because of charge compensation effect, and we obtained low on-state resistivity characteristic in the same breakdown voltage. In this paper, we analyzed on-state and off-state characteristics of SOI LIGBT with dual epi-layer. Breakdown voltage of proposed LIGBT was shown 125V when $T_1=T_2=2.5{\mu}m$, $N_1=7{\times}10^{15}/cm^3$ and $N_2=3{\times}10^{15}/cm^3$, respectively Although we used high doping concentration and thin epi-layer thickness, breakdown voltage was increased compared with conventional devices.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.288-291
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• 2004

Due to the charge compensation effect, SOI(Silicon-On-Insulator) LIGBT with dual-epi layer have been found to exhibit both low forward voltage drop and high static breakdown voltage. In this paper, electrical characteristics of the SOI LIGBT with dual-epi structure is presented. Trenched anode structure is employed to obtain uniform current flowlines and shorted anode structure also employed to prevent the fast latch-up. Latching current density of the proposed LIGBT with $T_1=T_2=2.5{\mu}m,\;N_1=7{\times}10^{15}/cm^3,\;N_2=3{\times}10^{15}/cm^3$ is $800A/cm^2$ and breakdown voltage is 125V while latching current density and breakdown voltage of the conventional LIGBT is $700A/cm^2$ and 55V.

• ETRI Journal
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• v.30 no.3
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• pp.347-354
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• 2008

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.2
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• pp.293-300
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• 2021

This study presents a Power Quality(:PQ) costs calculation methodology based on Value-Based Methodology. A SCDF including Voltage Sag Costs is presented to calculate Sustained Interruption Costs, Momentary Interruption Costs, and Voltage Sags Costs. Authors compared between interruption costs without Back-Up Power Supply and interruption costs with Back-Up Power Supply, and showed reduction of interruption costs by investing Back-UP Power Supply by multi-lateral analyzation. By applying this method to the real system, evaluated and analyzed power quality of the system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.449-457
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• 2012

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.13-21
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• 2014

Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.443-446
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• 1991

In the conventional current control methods for the current-type reactive power compensators, it is usual to compare the reactive reference current signal with the triangular wave and hence to generate the ON-OFF signals for the semiconductor reactive power compensator. To improve the response as well as the control capability, the delta modulated current control technique is proposed in this paper and studied theoretically.