• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1852-1854
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• 1998

In this paper, we design an effective and secure optical subscriber loop to offer multimedia service to apartment residents. The designed subscriber loop has the following properties. First, a proxy is connected to HDT(Host Digital Termination) which is a switching device, in order to effectively support multimedia services. Second, a scheduler of HDT dynamically manages bandwidth allocation and reallocation to a subscriber considering the situation of communication traffic. Finally, three alternations are used for safety.

• Journal of information and communication convergence engineering
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• v.16 no.2
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• pp.84-92
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• 2018

For large wireless sensor networks running on battery power, the time synchronization of all sensor nodes is becoming a crucial task for waking up sensor nodes with exact timing and controlling transmission and reception timing. However, as network size increases, this synchronization process tends to require long processing time consume significant power. Furthermore, a naïve synchronization scheduler may leave some nodes unsynchronized. This paper proposes a power-efficient scheduling algorithm for time synchronization utilizing the notion of density, which is defined by the number of neighboring nodes within wireless range. The proposed scheduling algorithm elects a sequence of minimal reference nodes that can complete the synchronization with the smallest possible number of hops and lowest possible power consumption. Additionally, it ensures coverage of all sensor nodes utilizing a two-pass synchronization scheduling process. We implemented the proposed synchronization algorithm in a network simulator. Extensive simulation results demonstrate that the proposed algorithm can reduce the power consumption required for the periodic synchronization process by up to 40% for large sensor networks compared to a simplistic multi-hop synchronization method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.1
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• pp.109-119
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• 2013

This paper presents the design of the Safety Programmable Logic Controller (SPLC) used in the Nuclear Power Plants, an analysis of a reliability for the SPLC using a markov model. The architecture of the SPLC is designed to have the multiple modular redundancy composed of the Dual Modular Redundancy(DMR) and the Triple Modular Redundancy(TMR). The operating system of the SPLC is designed to have the non-preemptive state based scheduler and the supervisory task managing the sequential scheduling, timing of tasks, diagnostic and security. The data communication of the SPLC is designed to have the deterministic state based protocol, and is designed to satisfy the effective transmission capacity of 20Mbps. Using Markov model, the reliability of SPLC is analyzed, and assessed. To have the reasonable reliability such as the mean time to failure (MTTF) more than 10,000 hours, the failure rate of each SPLC module should be less than $2{\times}10^{-5}$/hour. When the fault coverage factor (FCF) is increased by 0.1, the MTTF is improved by about 4 months, thus to enhance the MTTF effectively, it is needed that the diagnostic ability of each SPLC module should be strengthened. Also as the result of comparison the SPLC and the existing safety grade PLCs, the reliability and MTTF of SPLC is up to 1.6-times and up to 22,000 hours better than the existing PLCs.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.54-62
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• 2015

Although NAND flash-based SSD (Solid-State Drive) provides superior performance in comparison to HDD (Hard Disk Drive), it has a major drawback in write endurance. As a result, the lifetime of SSD is determined by the workload and thus it becomes a big challenge in current technology trend of such as the shifting from SLC (Single Level Cell) to MLC (Multi Level cell) and even TLC (Triple Level Cell). Most previous studies have dealt with wear-leveling or improving SSD lifetime regarding hardware architecture. In this paper, we propose the optimal configuration of host I/O stack focusing on file system, I/O scheduler, and link power management using JEDEC enterprise workloads in terms of WAF (Write Amplification Factor) which represents the efficiency perspective of SSD life time especially for host write processing into flash memory. Experimental analysis shows that the optimum configuration of I/O stack for the perspective of SSD lifetime is MinPower-Dead-XFS which prolongs the lifetime of SSD approximately 2.6 times in comparison with MaxPower-Cfq-Ext4, the best performance combination. Though the performance was reduced by 13%, this contributions demonstrates a considerable aspect of SSD lifetime in relation to I/O stack optimization.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.05a
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• pp.60-61
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• 2019

Drones are opening new horizon as a major Internet-of-Things (IoT) player which is a network of objects. Drone needs to charge itself during providing services from the charging stations. If there are lots of drones and one charging station, then it is a critical situation to decide which drone should get charged first and make order of priorities for drones to get charged sequentially. In this paper, we propose an efficient scheduling algorithm for drone power charging (ESADPC), in which charging station would have a scheduler to decide which drone can get charged earlier among many other drones. Simulation results have showed that our algorithm reduces the deadline miss ration and turnaround time.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.77-78
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• 2008

본 논문에서는 한국형 에너지 관리 시스템의 네트웍 해석 소프트웨어의 하나인 휴전계획 프로그램의 개발에 대해 다루었다. 휴전계획은 장단기의 계통 설비 휴전에 대한 데이터베이스 관리 프로그램으로 계통 해석용 소프트웨어들에 정보를 제공한다. 휴전계획 프로그램의 개발을 위해 현행 휴전 절차를 검토하였으며 이를 통해 사용자 요구사항을 반영한 데이터베이스를 설계하였다. 휴전 계획 프로그램의 특성상 여타의 다른 EMS 용 어플리케이션과 달리 화면 처리 및 휴전정보 처리를 위한 독립적인 실시간 어플리케이션과 데이터를 필요로 하므로 이를 위한 아키텍쳐를 설계하였다. C++ 및 ANCI C를 사용하여 구현하였으며 한국형 EMS 시스템의 실시간 환경하에서 시험하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.354-360
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• 2008

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System (OS) and existing hardware support.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.4
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• pp.2777-2783
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• 2015

Peak power reduction is becoming increasingly important not only for grid operators but also for residential users. The scheduling of electric loads tries to reduce the power peak by splitting the power-on period of an electric device into multiple smaller ones and by interleaving the on-periods of every device in a holistic way. This paper analyzes the performance of EDF, LSF, TCBM, and lazy scheduling algorithms and proposes the enhancement schemes. For analysis, we have implemented the scheduling policies in a simulation environment for distributed control systems. Through extensive experiments using real power traces, we discuss their performance characteristics in terms of power deviation, switch count, and temperature violation ratio. To prevent excessive switching, we propose to employ the concept of limited preemptibility and evaluate its effect on performance. It is found that the best performance is achieved when the scheduler capacity is dynamically adjusted to the actual power demand. The experiment results show that, by load scheduling, the probability of having a power deviation greater than 150W is reduced from 21.5% down to 3.2%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1608-1616
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• 2015

This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.