• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.1
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• pp.1-8
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• 2019

In this study, a maximum power point tracking (MPPT) algorithm based on the perturb and observe (P&O) method with variable step size is proposed to improve the dynamic response characteristic of MPPT, using the existing P&O method. The proposed algorithm, which we verified by simulation and experiment, can track the maximum power point (MPP) through duty control and consisted of three operation modes, namely, constant voltage mode, fast mode, and variable step mode. When the insolation is constant, the voltage variation of the operating point at the MPP is reduced through the step size reduction of the duty in the variable step mode. Consequently, the vibration of the operating point is reduced, and the power generation efficiency is increased. When the insolation changes, the duty and the photovoltaic (PV) voltage are kept constant through the constant voltage mode. The operating point then rapidly tracks the new MPP through the fast-mode operation at the end of the insolation change. When the MPP is reached, the operation is changed to the variable step mode to reduce the duty step size and track the MPP. The validity of the proposed algorithm is verified by simulation and experiment of a PV system composed of a PV panel and a boost converter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.719-725
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• 2019

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

• ETRI Journal
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• v.19 no.2
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• pp.35-47
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• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.4B no.2
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• pp.65-72
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• 2004

Switching power supply systems are widely used in many industrial fields. Power factor correction (PFC) circuits have a tendency to be applied in new power supply designs. The input active power factor correction (APFC) circuits can be implemented in either the two-stage approach or the single-stage approach. The two-stage approach can be classified into boost type PFC circuit and dc/dc converter. The power factor correction circuit with a boost converter used as an input power source is studied in this paper. In a boost power factor correction circuit there are two feedback control loops, which are a current feedback loop and a voltage feedback loop. In this paper, the regulation performance of output voltage and compensator to improve the transient response presented at the continuous conduction mode (CCM) of the boost PFC circuit is analyzed. The validity of designed boost PFC circuit is confirmed by MATLAB simulation and experimental results.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.8
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• pp.1495-1505
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• 2002

As combining the functions of a 2K-H B type differential gear unit and a V-belt type continuously variable unit(CVU), 16 different mechanisms are presented. Some useful theoretical formula related to speed ratio, power flow and efficiency are derived and analyzed. Continuously variable transmission(CVT) mechanisms are proposed, which can of ffr a backward mode, a geared neutral, an underdrive mode and an overdrive mode. They are not required of a starting device as a torque converter. CVT mechanisms developed here present two distinct operating modes which are a power circulation mode and a power split mode. The transition of two modes takes place at the particular CVU speed ratio. For these CVT mechanisms, performance analysis related to speed ratio, power ratio and theoretical efficiency are executed.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.133-138
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• 2014

This paper proposes a low power-loss averaging current mode control using a resistor and bypass switch. Generally, current sensing method using a resistor has a disadvantage of power loss which degrades the efficiency of the entire systems. On the other hand, proposed measurement technique operating with bypass-switch connected in parallel with sensing resistor can reduce power loss significantly the current sensor. An analog-circuited bypass driver is implemented and used along with an average-circuit mode controller. The bypass switch bypasses the sensing current with a small amount of power loss. In this paper, a 50[W] prototype average current mode boost converter has been implemented for the experimental verification.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.162-168
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• 2005

In this paper, a digital current mode control is designed for the power converter applications. The designed digital current mode controller is derived analytically from the continuous time small signal model of the power converters. Due to the small signal model based derivations of the control law, the designed control method can be applicable to boost, buck, and buck-boost converters. It is also proven that the controlled power converter employing the designed digital current mode controller is always stable regardless of an operating conditions. In order to show the usefulness of a designed controller, experiments are carried out using a 16bit DSP micro-processor, TMS320LF2406A.

• Journal of Power Electronics
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• v.10 no.2
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• pp.132-137
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• 2010

Interleaving techniques are widely used to reduce input/output ripples and to increase the power capacity of boost converters operating in critical conduction mode. Two types of phase-shift control schemes are studied in this paper, the turn-on time shifting method and the turn-off time shifting method. It is found that although the turn-off time shifting method exhibits better performance, it suffers from sub-harmonic oscillations at high input voltages. To solve this problem, an intensive quantitative analysis of the sub-harmonic oscillation phenomenon is made in this paper. Based upon that, a novel modified turn off time shifting control scheme for interleaved boost converters operating in critical conduction mode is proposed. An important advantage of this scheme is that both the master phase and the slave phase can operate stably in critical conduction mode without any oscillations in the full input voltage range. This method is implemented with a FPGA based digital PWM control platform, and tests were carried out on a two-phase interleaved boost PFC converter prototype. Experimental results demonstrated the feasibility and performance of the proposed phase-shift control scheme.