• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.278-281
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• 2014

This paper presents the performance comparison of three types of full-wave rectifiers for vibration energy harvesting. The first rectifier is consisted of two active diodes and two MOSFETs, and the comparators of the active diodes are powered from the output of the rectifier. The second one is a 2-stage full-wave rectifier. It comprises the basic rectifier consisted of four MOSFETs and an active diode. The comparator is also powered from the output of the rectifier. The third one is an input powered rectifier. It has the same structure as the second rectifier, but the comparator is powered from the input of the rectifier. These rectifiers have been designed using a 0.35um CMOS process and their performances have been compared through simulations. In terms of efficiency, the first rectifier shows the best performance at heavy loads, but the second one is suitable at light loads. When the power consumption during absence of vibration is more important than efficiency, the input-powered rectifier is proper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1609-1618
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• 2015

DC microgrids are considered as prospective systems because of their easy connection of distributed energy resources (DERs) and electric vehicles (EVs), reduction of conversion loss between dc output sources and loads, lack of reactive power issues, etc. These features make them very suitable for future industrial and commercial buildings' power systems. In addition, the bipolar-type dc system structure is more popular, because it provides two voltage levels for different power converters and loads. To keep voltage balanced in such a dc system, a bidirectional dual buck-boost voltage balancer with direct coupling is introduced based on P-cell and N-cell concepts. This results in greatly enhanced system reliability thanks to no shoot-through problems and lower switching losses with the help of power MOSFETs. In order to increase system efficiency and reliability, a novel burst-mode control strategy is proposed for the dual buck-boost voltage balancer. The basic operating principle, the current relations, and a small-signal model of the voltage balancer are analyzed under the burst-mode control scheme in detail. Finally, simulation experiments are performed and a laboratory unit with a 5kW unbalanced ability is constructed to verify the viability of the bidirectional dual buck-boost voltage balancer under the proposed burst-mode control scheme in low-voltage bipolar-type dc microgrids.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.563-566
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• 2009

This paper presents a motor drive IC for automotive applications. The drive IC is dedicated to control and drive external MOSFETs which directly drive 3-phase motor with a high current. In case of driving high-side power switches, the bootstrap topology is widely used. however, it requires three bootstrap diode and three capacitor respectively. And it needs a minimum charging time to maintain high-side voltage. The motor drive IC uses a charge-pump circuit for all three high-side voltage with various protection schemes for automotive applications.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.37-39
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• 2008

In this paper, a three-port bidirectional modular circuit applied in charging and discharging equalization for lithium-ion battery strings is proposed. This circuit consists of four MOSFETs and one transformer which provide a simple structure to be easily modularized. Compared to conventional individual cell equalization schemes, it utilizes the transformer as the energy transfer element, allowing direct transfer of energy between arbitrary two cells of three-cell battery module, thus improving the equalization efficiency significantly by using much less number of equalizers for long battery strings. Simulation results are presented to validate the circuit operation and confirm its capability to equalize the three-cell battery module.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.2
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• pp.105-110
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• 2012

This paper designs the high-efficiency and the low-cost drive system of the smallsize electric vehicles (EVs). The power circuit for driving the dc motor is designed by considering both the cost and efficiency. In order to reduce the conduction loss of MOTFET and diode for controlling an armature voltage, some MOSFETs and diodes at the armature are in parallel connection. An operating sequence for both the field current and the armature voltage according to the accelerator pedal angle is suggested for changing smoothly the rotating direction of dc motor. Through the simulation studies, the performances of the proposed methods are verified.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• Journal of Industrial Technology
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• v.24 no.A
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• pp.91-97
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• 2004

This paper describes the design of a 2-phase stepping motor driver using CPLD(Complex Programmable Logic Device). The driver IC such as L297(SGS-Thomson Microelectronics), which is mostly used has some difficulties in PWM control because of the switching noise of power MOSFETs. It causes current ripple and acoustic noise. To improve theses characteristics, we proposed a new current control method that the output PWM frequency is almost constant using a digital filter. Also we proposed constant current method for 1-2 phase(half step) excitation. The proposed method is implemented with CPLD(Xilinx, XC9572-PC44). Experimental results show the effectiveness of the proposed method.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.159-162
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• 2009

The necessity of radiation dosimeter with precise measurement of radiation dose is increased and required in the field of spacecraft, radiotheraphy hospital, atomic plant facility, etc. where radiation exists. Until now, a low power commercial metal-oxide semiconductor(MOS) transistor has been tested as a gamma radiation dosimeter. The measurement error between the actual value and the measurement one can occur since the MOSFET(MOS field-effect transistor) dosimeter, which is now being used, has two gates with same width. The measurement value of dosimeter depends on the variation of threshold voltage, which can be affected by the environment such as temperature. In this paper, a radiation dosimeter having a pair of MOSFET is designed in the same silicon substrate, in which each of the MOSFETs is operable in a bias mode and a test mode. It can measure the radiation dose by the difference between the threshold voltages regardless of the variation of temperature.