• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.11-12
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• 2009

In this paper, we propose a high voltage driver IC(HVIC) for LCD and PDP TV power supply. The proposed circuit is included novel a shoot-through protection and a pulse generation circuit for the high voltage driver IC. The proposed circuit has lower variation of dead time and pulse-width about a variation of a process and a supply voltage than a conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also the proposed pulse generation circuit prevent from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, and its variation is maximum 170 ns(68 %) about a variation of a process and a supply voltage. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD process parameter, and a simulation is carried out using Spectre.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.958-959
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• 2015

This paper proposes adaptive incremental conductance(A-IC) algorithm for maximum power point tracking(MPPT) control of photovoltaic. Conventional Perturbation & Observation(PO) and IC MPPT control algorithm generally uses fixed step size. A small fixed step size will cause the tracking speed to decrease and tracking accuracy of the MPP will decrease due to large fixed step size. Therefore, this paper proposes N-IC MPPT algorithm that adjust automatically step size according to operating conditions. To improve tracking speed and accuracy, when operating point is far from maximum power point(MPP), step size uses maximum value and when operating point is near from MPP, step size uses variable step size that adjust according to slope of P-V curve. The validity of MPPT algorithm proposed in this paper prove through compare with conventional IC MPPT algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1217-1220
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• 2003

A low-power design technique for lithium-ion Battery-Protection Integrated Circuit (BPIC) for multi cell configuration is proposed. The hardware sharing scheme with more precisely divided operating states in the detection range could reduce the power consumption significantly, especially during the normal state. The usefulness of the proposed scheme was confirmed through HSPICE simulations.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.301-302
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• 2005

A low-power gate driver IC, which can be used for TFT-LCD application, is proposed. The short-circuit current of the output buffer is greatly reduced. An experimental prototype gate driver implemented in a $0.35-{\mu}m$ CMOS technology demonstrates that the power reduction of 16 % is obtained.

• Journal of information and communication convergence engineering
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• 제12권1호
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.321-324
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• 2004

This paper presents a package IC containing some components of DC/DC converter block for mobile phone's sub OLED(Organic Light Emitting Display). Package IC contains a load switch, a control IC, a diode, a switch for on/off operation, and a switch for changing output voltage. It operates with switching frequency of 100kHz, within the range of input voltage, $3.2V\~5.5V$. Duty ratio can be changed up to $93\%$, and maximum power efficiency is $85\%$. This package IC is loaded onto three model of 1.2W mobile phone's sub-OLED.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.937-940
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• 2000

This paper describes expandable 4 bit ALU IC using adiabatic and dynamic CMOS circuit technique. It was designed so that the integrated circuit may have the function which is equivalent to HC181 which is CMOS standard logic IC for the comparison, and it was fabricated using a standard 1.2${\mu}$ CMOS process. As the result, the IC has shown that it operates perfectly on all function modes. The power dissipation is 2 order lower than that of HC 181.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2039-2041
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• 2001

According to the deregulation of governments in the world, the power industries of United State and European nations are proceeding remote meter reading and remote load control. But the core technology of multifunctional electronic meter implemented by programmable one-chip IC, which can be the right answer of ail the power industy's efforts is now still under development in the advanced countries. Implementation of smallest size, lowest price three-phase meter with features which enable distribution automation such as bidirectional communication. The three phase metering IC and meter can be used as metering, automatic meter reading and transformer monitoring. Prepayment billing system.

• ETRI Journal
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• 제36권4호
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기물성,응용부문
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• pp.57-59
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• 2005

전력용 IC에서 높은 항복전압의 구현을 위해서 RESURF구조가 많이 사용되고 있다. 하지만 하나의 칩 위에서 다양한 항복전압을 가지는 소자를 구현하기 위해서는 에피층의 농도가 각각 달라져야하는데 이는 공정상의 복잡함과 비용의 문제를 수반하게 된다. 이런 문제점에 따라 본 연구에서는 전력용 IC에서 항복전압이 다른 다수의 LDMOST를 추가 공정없이 에피 영역의 길이를 조절하여 구현할 수 있음을 해석적인 방볍과 2차원 소자 시뮬레이터를 이용하여 확인하였다.