• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.15-22
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• 2004

This paper presents the channel analysis considering power distribution network(PDN) system of PCB. For achieve the target PDN system we proposed the useful design approach for acquiring the characteristic target of power distribution network in overall frequency ranges. The proposed method is based on the hierarchical approach related to frequency ranges and the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors and the board through it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. The analysis of PDN system shows that although the effective inductance of package dominatly affects the power noise and the signal transfer through data channel, the board PDNs also can not be neglected for achieving the accurate channel signaling. Therefore, we must design concurrently the chip, package, and board from the initial spec design of high speed digital system.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.41-45
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• 2013

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.110-120
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• 2010

In this paper, we propose a tunable SIW(Substrate Integrated Waveguide) using dielectric screws for eliminating the phase imbalance of large size power distribution networks(PDN). Alumina screws partially inserted into several through holes of the tunable SIW section effectively change the phase shift without S-parameter degradation. ${\pm}33.9^{\circ}$ measured phase imbalance of a large conventional 9 GHz SIW-PDN of $370\;mm{\times}195\;mm$ size has been greatly reduced to ${\pm}4.65^{\circ}$. We expect that the proposed tunable SIW plays an important role for a light-weight, high performance substrate integrated phased array system(Si-PAS) and large size SIW circuit applications.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.11
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• pp.1988-1991
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• 2007

This study investigates the performances of the signaling techniques including differential signals for the power-distribution network(PDN)s with and without the slit, using a rigorous evaluation method 'Modal Analysis', validated by being compared to the FDTD simulation up to 5 GHz.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.130-131
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• 2007

This study investigates the performances of the signaling techniques including differential signals for the power-distribution network(PDN)s with and without the slit, using a rigorous evaluation method, validated by the FDTD simulation up to 5 GHz.