• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.9 no.4
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• pp.124-130
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• 2010

This paper considers a power saving technique of set-top box (STB) that turns the signal into content which is then displayed on the television (TV) screen. A traditional power saving scheme, Auto Power Down (APD), was devised to reduce the power consumption of STB. APD checks whether the user is watching TV over a period of time and enforces STB into stand-by mode when the check result reveals the user is not watching TV. This paper proposes an enhanced power saving scheme that transits STB operation mode to 'stand-by' immediately when STB recognizes the change of TV's external input signal. The proposed scheme does not require the monitoring time to check the users' watching TV, and transits to standby mode faster than the conventional APD, which results in better performance in power saving. The simulation result shows that the proposed scheme achieves 2 to 11% improvement in power consumption compared with the conventional APD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.845-848
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• 2010

After analyzing various information gathered in Wireless Sensor Networks, it is sent to the node far from it. If it fails to keep its minimum power considering power consumption, the node and the network wouldn't work. There are many research that each node gets the power from solar cells and keep the life to maximize networks'life thus solar cells should be modeled considering power consumption. This thesis propose the fit model of solar cells considering charge and discharge in Wireless Sensor Networks.

• Journal of IKEEE
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• v.23 no.4
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• pp.1373-1380
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• 2019

In order to increase energy efficiency, developments of the advanced metering infrastructure (AMI) in the smart grid technology have recently been actively conducted. An essential part of AMI is analyzing power consumption and forecasting consumption patterns. In this paper, we analyze the power consumption and summarized the data errors. Monthly power consumption patterns are also analyzed using the k-means clustering algorithm. Forecasting the consumption pattern by each household is difficult. Therefore, we first classify the data into 100 clusters and then predict the average of the next day as the daily average of the clusters based on the deep neural network. Using practically collected AMI data, we analyzed the data errors and could successfully conducted power forecasting based on a clustering technique.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.713-716
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• 2008

This paper presents an automatic back-light brightness control system for mobile displays. One of the most important factors in mobile display is the power consumption due to the limited and movable power source. More than 80% of power of the LCD display is consumed by LED bark-light unit (BLU). The target brightness also becomes higher because of its moving picture and high resolution image, so there are some side effects for not only excessive power consumption but also ergonomic inconvenience in dark environment. To prevent this discomfort and reduce power consumption, this paper proposes automatic brightness control (ABC) technique in mobile displays. Developed system contains TFT-LCD panel with built-in photo sensor, driver IC capable of controlling photo sensor, and BLU. Since the photo sensor array built in panel detects automatically outdoor ambient light intensity, the power of BLU in dark environment is reduced. Developed ABC system showed reduced power consumption of 50% in dark environment. We believe that the proposed system is very useful to control power of mobile TFT-LCD.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.122-129
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• 2014

Due to remarkable market growth of smart devices, higher performance and more functionalities are required for a core system-on-chip (SoC), and thus the power demand is rapidly increasing. However, aggressive shrink of CMOS transistor have brought severe process variations thereby adversely affected the performance and power consumption under strict power constraint. Voltage binning (VB) scheme is one of the effective post silicon tuning techniques, which can reduce parametric yield loss due to process variations by adjusting supply voltage. In this paper, an optimal supply voltage tuning based voltage binning technique is proposed to reduce average power without an additional yield loss. Considering the different LVCC margins of process corners along with speed and leakage characteristics, the proposed method can optimize the deviation of voltage margin and thus save power consumption. When applying on a 30nm mobile SoC product, the experimental results showed that the proposed technique reduced average power consumption up to 6.8% compared to traditional voltage binning under the same conditions.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.438-440
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• 2004

Energy consumption has become an increasingly important consideration in designing real-time embedded systems. In this paper, we propose a voltage scaling method to reduce energy consumption in fixed priority real-time systems using variable voltage processors. The Hyperperiod of tasks is divided into dimains. The most suitable voltage of each domain is determined off-line and stored in a table. During task execution, the voltage of processor is adjusted according to the information of the table. A simulation result shows that the proposed method can reduce 80% of power consumption in comparison to no power management. The difference to the optimal EDF based method is only 5%.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.75-78
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• 2000

This paper presents a new algorithm for allocating the data path to achieve the minimum power consumption under the constraints of minimum hardware resources. In order to minimize the power consumption, the proposed algorithm tries to minimize the input transitions of functional units, unnecessary computations, and size of interconnects in a greedy manner during a]location. Experimental results using benchmarks indicate the proposed algorithm achieves 17.5% power reduction on average, when compared with the genesis-lp［1］high-level synthesis system.

• Journal of KIISE
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• v.44 no.9
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• pp.954-965
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• 2017

A stable power supply is very important for the maintenance and operation of the power infrastructure. Accurate power consumption prediction is therefore needed. In particular, a university campus is an institution with one of the highest power consumptions and tends to have a wide variation of electrical load depending on time and environment. For this reason, a model that can accurately predict power consumption is required for the effective operation of the power system. The disadvantage of the existing time series prediction technique is that the prediction performance is greatly degraded because the width of the prediction interval increases as the difference between the learning time and the prediction time increases. In this paper, we first classify power data with similar time series patterns considering the date, day of the week, holiday, and semester. Next, each ARIMA model is constructed based on the classified data set and a daily power consumption forecasting method of the university campus is proposed through the time series cross-validation of the predicted time. In order to evaluate the accuracy of the prediction, we confirmed the validity of the proposed method by applying performance indicators.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.4
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• pp.17-23
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• 2012

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.2
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.