• 전기학회논문지
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• 제60권2호
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• pp.320-324
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• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1117-1118
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• 2008

The LightScribe Technology is for printing images on the label side of recordable media using CD laser diode. By implementing Optimum Labeling Power Calibration for LightScribe, Labeling Quality can be improved. This paper proposes a new laser power calibration method using RFSUM signal. This function is implemented based on GH22LP20 of LG Electronics.

• 전기학회논문지
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• 제59권5호
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• pp.1005-1009
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• 2010

This paper presents a digitally-controlled filter calibration technique for biquad RC filter using self oscillation. The biquad RC filter is converted to a fully-differential ring oscillator by changing its resistor connections, where the oscillation frequency reflects the cut-off frequency. The proposed calibration circuit measures the oscillation frequency by counting with a fixed higher-frequency clock and then tunes it to a desired frequency with a digital frequency-locked loop including a PI controller. Because the proposed circuit directly measures the cut-off frequency of the filter itself and calibrates it with the small area digital circuits, the area and the power consumption are much small compared with conventional works. When it is implemented in a 65nm CMOS process, the calibration circuit except the filter consumes the area of 80um X 50um and power consumption is 443uA at 1.2 V supply voltage.

• 동력기계공학회지
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• 제12권4호
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• pp.18-25
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• 2008

This paper investigated the new calibration algorithm of a straight-type five-hole pressure probe necessary for calculating three-dimensional flow velocity components. The new data reduction method Includes a look-up, a geometry transformation such as the translation and reflection of nodes, and a binary search algorithm. This new calibration map was applied up to the application angle, ${\pm}55^{\circ}$ of a probe. As a result, this data reduction method showed a perfect performance without any kind of interpolation errors In calculating yaw and pitch angle from the calibration map.

• 한국자동차공학회논문집
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• 제24권3호
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• pp.319-329
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• 2016

Globally, many researchers have been trying to improve the fuel economy of a vehicle for satisfying future $CO_2$ regulation and minimizing air pollution problem. For the same background, diesel engine and vehicle system optimization using simulation models have been key technologies for the improvement of vehicle system efficiency. Therefore, in this study, calibration method for the air breathing system of a WGT diesel engine using mean value model has been composed for efficient engine and vehicle optimization simulation researches. And virtual WGT performances have been calculated for a 2 cylinder downsized diesel engine system. From these researches, the calibration method for the boost pressure and EGR rate of a virtual diesel engine related with WGT performances could be composed and some of technical issue related with downsized diesel engine could be investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• 대한전자공학회논문지SD
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• 제47권3호
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• pp.18-27
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• 2010

본 논문에서는 offset self-calibration 기법을 적용한 7-bit 1GSPS folding-interpolation A/D 변환기를 제안한다. 제안하는 A/D 변환기는 folding rate 2, interpolation rate 8의 1+6 구조로 고속 동작에 적합하게 설계되었다. 또한 offset self-calibration 회로를 설계하여 공정 mismatch, 기생 저항, 기생 캐패시턴스 등에 의한 offset-voltage의 변화를 감소시켜 A/D 변환기의 성능 특성을 향상 시켰다. 제안하는 A/D 변환기는 1.2V 65nm 1-poly 6-metal CMOS 공정을 사용하여 설계 되었으며 유효 칩 면적은 $0.87mm^2$, 1.2V 전원전압에서 약 110mW의 전력소모를 나타내었다. 측정 결과 샘플링 주파수 800MHz, 입력 주파수 250MHz에서 39.1dB의 SNDR 특성을 보여주었으며, offset self-calibration 회로를 사용 하지 않은 A/D 변환기에 비해 SNDR이 약 3 dB 향상되었다.

• 한국음향학회지
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• 제43권3호
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• pp.344-350
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• 2024

기준음원은 음향파워 측정에 활용되는 중요한 기준기로, 국제 표준으로 그 사양이 규정되어 있으며, 측정 표준 분야에서 주요 교정 품목으로 분류되고 있다. 이러한 기준음원은 공급 전압에 의하여 그 출력이 영향을 받기 때문에 각국에서 자체적으로 교정 서비스 체계를 확보할 필요가 있다. 본 연구에서는 잔향실 조건에서 기준음원을 교정하는 절차를 수립하고 불확도를 평가하였다. 교정 절차는 기본적으로 음향 파워의 정밀급 측정과정을 적용할 수 있으며, 여기서는 ISO 3741의 잔향실을 활용한 측정 방법을 검토하였다. 이를 위한 측정 시스템을 구성하고 실제 2종의 기준 음원에 대하여 측정을 수행하고 측정 불확도를 산출하였다. 측정 예를 통하여 잔향실 내 음압 분포의 불균일성과 체적 측정 불확도가 전체 불확도에 기여가 큰 것을 확인하였다. 추가적으로 입력 전압에 대한 영향을 실험적으로 검토하여 음향 파워 측정에서 반영할 수 있는 불확도 기여량을 검토하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.274-286
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• 2016

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

• The Journal of Korean Physical Therapy
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• 제23권3호
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• pp.37-42
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• 2011

Purpose: The principal objective of this study was to evaluate the power output of ultrasound in Korean clinics and compare the value with Korean and global standards. Methods: A total of 69 units were measured for ultrasound power output. The normal range of power output level was ${\pm}30%$ of the output set according to KFDA standards. Device model, manufacturer, ERA, and BNR were obtained via simple questionnaires. A portable ultrasound power meter was used for output measurement. Results: 37 machines, with reported ERA values, were assessed for power output per unit area. Of these machines, 13 (37.14%) were considered to be compliant with US FDA standards at 0.5, 1.0, 1.5, $20W/cm^2$ and 18 (51.43%) were considered within KFDA standards. The remainder of the machines were outside the standard error and evidenced irregular output levels, even though most of them were the same model. Conclusion: Appropriate ultrasound intensity is incredibly important for safety and effective use. Therefore, the KFDA standards regarding ultrasound may require revision in light of global standards, including BNR and ERA additionally, attention should be paid to regular calibration for safe use in clinical practice.