• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.229-232
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• 2001

4H-SIC(silicon carbide) MESFET large signal model was studied using modified Materka-Kacprzak large signal MESFET model. 4H-SiC MESFET device simulation have been conducted by Silvaco's 2D device simulator, ATLAS. The result is modeled using modified Materka large signal model. simulation and modeling results are -8V pinch off voltage, under $V_{GS=0V}$, $V_{DS=25V}$ conditions, $I_{DSS=270㎃}$mm, $G_{m=45㎳}$mm were obtained. Through the power simulation 2GHz, at the bias of $V_{GS=-4V}$ and $V_{DS=25V}$, 10dB Gain, 34dBm(1dB compression point)output power, 7.6W/mm power density, 37% PAE(power added efficiency) were obtained.d.d.d.

• Journal of Korean Society for Atmospheric Environment
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• v.14 no.4
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• pp.333-342
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• 1998

Plasma process has great possibilities to remove SOx, NOx simultaneously with high treatment efficiency and is expected to be suitable for small or middle plants. It was accomplished to evaluate SO2, NOx control possibility and achieve basic data to control pollutants by use of Surface Discharge Induced Plasma Chemical Process (SPCP) in this study. O3 generation characteristics by discharge of a plate was proportional to O2 concentration and power consumption and inversely proportional to temperature and humidity, In case of dry air, NOx was highly generated by N2 and O2 in air during the plasma discharge process but it was decreased considerably as H2O was added. SO2 removal efficiency was very high, and removal rate was 170,350 mEA at 30,50 watt respectively in flue gas which is usually contain HIO. NOx removal efficiency was about 57% at 40 watt power consumption with 7.5% humidity. It is estimated that H2O has an important role in reaction mechanism with pollutants according to plasma discharge.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.480-484
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• 1999

In this paper, a design technique of SMPS using plannar transformer is described. The application of plannar transformer can solve the space problem which occurs when it is installed on PCB since plannar transformer has low profile. In addition a lossless snubber circuit added to reduce the device stress and to improve the system efficiency. The designed system is verifed by simulation and experiment with comparison of efficiency between the system using conventional transformer and the system using plannar transformer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.4
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• pp.323-331
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• 1997

In this paper, the high efficiency balanced amplifier is presented as high efficiency power amplifier. This amplifier is basically composed of two FETs, an input power divider, output power combiner, input matching circuits, output matching circuits, second harmonic interconnection circuit and lowpass filter. The second harmonic interconnection circuit is composed of second harmonic frequency bandpass filter and transmission line. This circuit is inserted between the output terminals of the two FEF's output matching circuit, there is a second harmonic standing wave generated between two FET outputs. The electric wall termination is equivalent to the short circuit termination. As a result, the FET output termination condition needed to attain high efficiency is realized. Experimental high efficiency balanced amplifier is constructed to determine its practically attainable efficiency. The input VSWR is 1.27, and the output VSWR is 1.18. Power added efficiency of 75% is attained at 1.75 GHz band about 3W to balanced amplifier.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.52-53
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• 2015

This paper introduces a novel hybrid converter combining a full-bridge soft switching converter and a full-bridge LLC converter. In this topology all the primary switches can achieve ZVS and ZCS all over the operation range. An additional switch and a diode are added in the secondary side of full-bridge converter to eliminate the circulating current and to provide a separate freewheeling path. The hybrid structure makes it possible to deliver the power to the secondary all the time of operation, thereby improving the efficiency. The proposed topology is suitable for the applications such as on-board chargers for electric vehicles and high power dc-dc converters. A 6.6-kW prototype converter was implemented and 97.5% efficiency was obtained through the experiments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1065-1071
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• 2010

In this paper, we proposed a novel harmonic load circuit to design a high efficiency class-F amplifier. The proposed load circuit controls termination impedances to enhance the efficiency of class-F power amplifier. The termination impedances at the 2nd and the 3rd harmonics are showed short and open condition, respectively. Also, a fabricated load circuit showed an attenuation characteristic more than 29 dB, that is enough to eliminate harmonics of the class-F power amplifier. The measured drain and power-added efficiency are 75.7 % and 71.3 % at the point of maximum output power 35.17 dBm.

• Journal of electromagnetic engineering and science
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• v.17 no.4
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• pp.221-227
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• 2017

A new approach to designing a broadband and highly efficient class-E power amplifier based on nonlinear shunt capacitance analysis is proposed. The nonlinear shunt capacitance method accurately extracts optimum class-E power amplifier parameters, including an external shunt capacitance and an output impedance, at different frequencies. The dependence of the former parameter on the frequency is considered to select an optimal value of external shunt capacitor. Then, upon determining the latter parameter, an output matching network is optimized to obtain the highest efficiency across the bandwidth of interest. An analytical approach is presented to design the broadband class-E power amplifier of a MOSFET transistor. The proposed method is experimentally verified by a 140-170 MHz class-E power amplifier design with maximum added power efficiency of 82% and output power of 34 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.966-974
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• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

• Journal of IKEEE
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• v.20 no.3
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• pp.279-284
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• 2016

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.162-170
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• 2004

A 900MHz CMOS RF power amplifier with digitally controllable output power has been proposed and designed with 0.6${\mu}{\textrm}{m}$ standard CMOS technology. The designed power amplifier was composed of digitally controllable switch mode pre-amplifiers with an integrated 4nH spiral inductor load and class-C output stage. Especially, to compensate the 1ow Q of integrated spiral inductor, cascode amplifier with a Q-enhancement circuit is used. It has been shown that the proposed power control technique allows the output power to change from almost 3dBm to 13.5dBm. And it has a maximum PAE(Power Added Efficiency) of almost 55％ at 900MHz operating frequency and 3V power supply voltage.