• Journal of the Korean Ceramic Society
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• v.32 no.7
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• pp.761-768
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• 1995

Double layered BaTiO3 thin films with high dielectric constant as well as good insulating property were prepared for the application to low voltage driving thin film electroluminescent (TFEL) device. BaTiO3 thin films were formed by rf-magnetron sputtering technique. Amorphous and polycrystalline BaTiO3 thin films were deposited at the substrate temperatures of room temperature and 55$0^{\circ}C$, respectively. Two kinds of films prepared under these conditions showed high resistivity and high dielectric constant. The figure of merit (=$\varepsilon$r$\times$Eb.d) of polycrystalline BaTiO3 thin film was very high (8.43$\mu$C/$\textrm{cm}^2$). The polycrystalline BaTiO3 showed a substantial amount of leakage current (I), under the high electric field above 0.5 MV/cm. The double layered BaTiO3 thin film, i.e., amorphous BaTiO3 layer coated polycrystalline BaTiO3 thin film, was prepared by the new stacking method and showed very good dielectric and insulating properties. It showed a high dielectric constant fo 95 and leakage current density of 25 nA/$\textrm{cm}^2$ (0.3MV/cm) with the figure of merit of 20$\mu$C/$\textrm{cm}^2$. The leakage current density in the double layered BaTiO3 was much smaller than that in polycrystalline BaTiO3 under the high electric field. The saturated brightness of the devices using double layered BaTiO3 was about 220cd/$m^2$. Threshold voltage of TFEL devices fabricated on double layered BaTiO3 decreased by 50V compared to the EL devices fabricated on amorphous BaTiO3.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.

• Journal of the Korean institute of surface engineering
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• v.53 no.3
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• pp.109-115
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• 2020

In this study, polycrystalline diamond was synthesized by chemical vapor deposition (CVD). Diamond films were deposited on a-plane sapphire substrates while changing the concentration of methane for hydrogen (CH₄/H₂), and the concentrations of methane were 0.25, 0.5, 1, 2, 3 and 4 vol%, respectively. Crystallinity and nucleation density according to changes in methane concentration were investigated. At this time, the discharge power, vacuum pressure, and deposition time were kept constant. In order to deposit polycrystalline diamond, the sapphire substrate was etched with sulfuric acid and hydrogen peroxide (ratio 3:7), and the sapphire surface was polished for 30 minutes with 100 nm-sized nanodiamond particles. The deposited diamond thin film was analyzed by a scanning electron microscope (SEM), a Raman spectra, Atomic force microscope (AFM) and an X-ray diffractometer (XRD). By controlling the ratio of methane to hydrogen and performing appropriate pre-treatment conditions, a polycrystalline diamond thin film having excellent crystallinity and nucleation density was obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.92-92
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• 2008

The surface flatness of heteroepitaxially grown 3C-SiC thin films is a key factor affecting electronic and mechanical device applications. This paper describes the surface flatness of polycrystalline 3C-SiC thin films by the gas flow control according to the location change of geometric structure. The polycrystalline 3C-SiC thin film was deposited by APCVD(Atmospheric pressure chemical vapor deposition) at $1200^{\circ}C$ using HMDS(Hexamethyildisilane : $Si_2(CH_3)_6)$ as single precursor, and 5 slm Ar as the main flow gas. According to the location of geometric structure, surface fringes and flatness changed. It shows the distribution of thickness is formed uniformly in the specific location of the geometric structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.408-409
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• 2006

The polycrystalline 3C-SiC thin films heteroepitaxially grown by LPCVD method using single precursor 1. 3-disilabutane at $850^{\circ}C$. The crystallinity of the 3C-SiC thin film. was analyzed by XPS. Residual strain was investigated by Raman scattering. The surface morphology and voids between SiC and $SiO_2$ were measured by SEM. The grown poly 3C-SiC thin film is very good crystalline quality, surface like mirror, and low defect and strain. Therefore, the polycrystalline 3C-SiC is suitable for harsh environment MEMS applications.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.12 s.177
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• pp.170-174
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• 2005

A numerical system to extract effective elastic properties of polycrystalline thin-films for MEMS devices is developed. In this system, the statistical model based on lattice system is used for modeling the microstructure evolution simulation and the key kinetics parameters of given micrograph, grain distributions and deposition process can be extracted by inverse method proposed in the system. In this work, effects of kinetics parameters on the extraction of effective elastic properties of polycrystalline thin-films are studied by using statistical method. Effects of the fraction of the potential site($f_p$) among the parameters for deposition process of microstructure on the extraction of effective elastic properties of polycrystalline thin-films are investigated. For this research, polysilicon is applied to this system as the polycrystalline thin-films.

• Journal of Sensor Science and Technology
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• v.16 no.2
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• pp.85-90
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• 2007

This paper presents the growth conditions and characteristics of polycrystalline 3C-SiC (silicon carbide) thin films for M/NEMS applications related to harsh environments. The growth of the 3C-SiC thin film on the oxided Si wafers was carried out by APCVD using HMDS (hexamethyildisilane: $Si_{2}(CH_{3})_{6})$ precursor. Each samples were analyzed by XRD (X-ray diffraction), FT-IR (fourier transformation infrared spectroscopy), RHEED (reflection high energy electron diffraction), GDS (glow discharge spectrometer), XPS (X-ray photoelectron spectroscopy), SEM (scanning electron microscope) and TEM (tunneling electro microscope). Moreover, the electrical properties of the grown 3C-SiC thin film were evaluated by Hall effect. From these results, the grown 3C-SiC thin film is very good crystalline quality, surface like mirror and low defect. Therefore, the 3C-SiC thin film is suitable for extreme environment, Bio and RF M/NEMS applications in conjunction with Si fabrication technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.8
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• pp.732-736
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• 2006

This paper describes the physical characterizations of polycrystalline 3C-SiC thin films heteroepitaxially grown on Si wafers with thermal oxide, In this work, the 3C-SiC film was deposited by LPCVD (low pressure chemical vapor deposition) method using single precursor 1, 3-disilabutane $(DSB:\;H_3Si-CH_2-SiH_2-CH_3)\;at\;850^{\circ}C$. The crystallinity of the 3C-SiC thin film was analyzed by XPS (X-ray photoelectron spectroscopy), XRD (X-ray diffraction) and FT-IR (fourier transform-infrared spectometers), respectively. The surface morphology was also observed by AFM (atomic force microscopy) and voids or dislocations between SiC and $SiO_2$ were measured by SEM (scanning electron microscope). Finally, residual strain was investigated by Raman scattering and a peak of the energy level was less than other type SiC films, From these results, the grown poly 3C-SiC thin film is very good crystalline quality, surface like mirror, and low defect and strain. Therefore, the polycrystalline 3C-SiC is suitable for harsh environment MEMS (Micro-Electro-Mechanical-Systems) applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.