• 산업기술연구
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• 제2권
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• pp.13-19
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• 1982

Polycrystalline silicon layers have been deposited by a chemical vapor deposition technique using $SiCl_4$, $H_2$ gas mixture on single crystal silicon substrates. In this work, the effects of depostion temperature and total flow rate on the deposition rate of polycrystalline silicon are investigated. From the experimental results it was found that the formation reaction of polycrystalline silicon was limited by surface reaction and mass transfer controlled as the deposition temperature was increased. The morphology of polycrystalline silicon layer changed from a fine structure to a coarse one as the deposition temperature was increased.

• 전자공학회논문지A
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• 제29A권2호
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• pp.55-62
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• 1992

Polycrystalline silicon ingots were manufactured using the casting method for polycrystalline silicon solar cells. These ingots were cut into wafers and ten n$^{+}$p type solar cells were made through the following simple process` surface etching, n$^{+}$p junction formation, metalization and annealing. For the grain boundary passivation, the samples were oxidized in O$_2$ for 5 min. at 80$0^{\circ}C$ prior to diffusion in Ar for 100 min. at 95$0^{\circ}C$. The conversion efficiency of polycrystalline silicon solar cells made from these wafers showed about 70-80% of those of the single crystalline silicon solar cell and superior conversion efficiency, compared to those of commercial polycrystalline wafers of Wacker Chemie. The maximum conversion efficiency of our wafers was indicated about 8%(without AR coating) in spite of such a simple fabrication method.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.75-76
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• 2006

In this paper, the polycrystalline silicon photodiodes utilizing vertically directed current path are investigated. The location of electrodes is considered with the grain direction and the current path. The relationships between grain boundaries and characteristics of photodiode are simulated to apply the vertically grown polycrystalline silicon to photodiodes. From the results, the vertically grown polycrystalline silicon photodiode is a potential candidate for CMOS image sensor. However, the increment of dark current related to grain boundaries should be reduced.

• 센서학회지
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• 제5권1호
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• pp.71-77
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• 1996

마이크로머시닝의 구조재료인 다결정 Si이 희생산화막의 영향을 받음을 고려하여 다결정 Si을 열산화시킨 다결정-산화막을 새로운 희생산화막의 재료로서 제안하고 평가하였다. 다결정-산화막상에 성장시킨 다결정 Si은 통상의 희생산화막상에 성장시키는 경우보다 grain size가 증가하였고, XRD결과를 통해 (111) texture의 증가와, 부가적인 (220) texture가 형성됨을 관찰하였다. 또한, 다결정-산화막상에 성장시킨 다결정 Si의 경우, 그 응력이 작고 균일한 분포를 나타내었다.

• 한국표면공학회지
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• 제43권1호
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 추계학술대회 초록집
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• pp.49.1-49.1
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• 2010

본 연구에서는 증착법에 의해 제조된 다결정 실리콘을 이용한 태양전지 제작과 관련하여 다결정 실리콘 씨앗층 제조를 위한 기판에 대하여 연구를 수행하였다. 다결정 실리콘 씨앗층을 제조할 수 있는 기술중 aluminum-induced layer exchange(ALILE) 공정을 이용하여 다결정 실리콘 씨앗층을 제조하였다. glass/Al/oxide/a-Si 구조로 알루미늄과 비정질 실리콘 계면에 알루미늄 산화막을 다양한 두께로 형성시켜, 알루미늄 유도 결정화에서 산화막의 두께가 결정화 특성에 미치는 영향, 결정결함, 결정크기에 대하여 연구하였다. 형성된 다결정 실리콘 씨앗층 막의 특성은 OM, SEM, FIB, EDS, Raman spectroscopy, XRD, EBSD 을 이용하여 분석하였다. 그 결과 산화막의 두께가 증가할수록 결함도 함께 증가하였다. 16nm 두께의 산화막 구조에서 <111> 방향의 우선배향성을 가진, $10{\mu}m$의 sub-grain 결정립을 갖는 씨앗층을 제조 하였다.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.

• 지식경영연구
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• 제12권1호
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• pp.39-52
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• 2011

Many LCD manufacturers continue to develop the technologies of LCD manufacturing processes for the reduction of production cost, power consumption and high-resolution. The LTPS (Low Temperature Polycrystalline Silicon) crystallization technology is important for rearranging the internal structure of liquid crystal grain by adding certain energy to amorphous silicon and turning it into poly-silicon in order to manufacture LCD with better performance. We consider 14 existing technologies of LTPS crystallization in the LCD manufacturing and present an intelligent analysis methodology using patent map and AHP (Analytic Hierarchy Process) analysis for determining an optimal LTPS crystallization technology. By using patent map analysis, we easily understand the development process and mega-trend of LTPS crystallization technologies and their relationship. By using AHP analysis, we evaluate 14 LTPS technologies. Through the use of proposed methodology, we determine the Continuous Wave Laser Lateral Crystallization technology as an optimal one.