• 한국광학회지
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• 제10권5호
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• pp.419-423
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• 1999

측면 연마된 단일모드 광섬유와 다중모드 폴리머 평면도파로 사이의 소산장 결합을 이용한 광필터를 제작하고 그 특성을 측정하였다. 소자의 편광의존성을 줄일 수 있는 방법 제안하였으며 실험으로 검증하였다. 그리고 광필터의 공진파장과 여과 깊이는 평면도파로의 두께와 연마깊이로서 적절히 선택할 수 있음을 실험으로 보였다. 광섬유 연마과정, 폴리머 평면도파로 제작 등을 포함한 소자제작 공정을 소개하였다. 제작된 광필터의 3㏈대역폭은 15nm, 삽입손실은 0.2㏈, 편광에 따른 공진 파장의 차이는 2nm 이하였다. 그리고 주위온도에 의한 공진파장의 이동거리는 -0.35nm/$^{\circ}C$로 측정되었다.

• 한국정밀공학회지
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• 제21권10호
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• pp.26-33
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• 2004

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffness equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1 st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave pronto because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.98-101
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive. the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, 1st, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the flatness of the ground wafer. Generally, the ground wafer has concave profile because of the difference of wheel path density, grinding temperature and elastic deformation of the equiptment. Tilting mathod is applied to avoid such non-uniform material removes. So, in this paper, the geometric analysis on grinding process is carried out, and then, we can predict the profile of th ground wafer by using profile simulation.

• Journal of Welding and Joining
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• 제19권2호
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• pp.191-199
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• 2001

The oxidation and recrystallization behaviors of Ni-base single crystal superalloy, CMSX-2 were investigated to determine the condition of the preparation for transient liquid phase (TLP) bonding operations. The faying surfaces of CMSX-2 were worked by the shot peening, fine cutting and mechanical polishing treatments and the degree of working of treated surfaces was evaluated by the hardness test and X-ray diffraction method CMSX-2 was heat-treated at 1,173∼1.589k for 3.6ks in vacuum of 4mPa. The mechanically polished surface was slightly oxidized after heat treatment even in the vacuum atmosphere of 4mPa. The thickness of an oxide film increased with increasing the heating temperature and the surface roughness of the faying surface. Recrystallization occurred at the surface after heat treatment at above 1,423K when the hardness was increased more than Hv600 by the shot peening treatment while the mechanically polished or fine cut surfaces didn't recrystallized. Based on these results, it was clearfied that the mechanically polishing with fine abrasive grit could be used for the preparation of faying surface of CMSX-2 before bonding operation.

• 열처리공학회지
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• 제2권2호
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• pp.33-37
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• 1989

In order to improve hardness uniformity of standard-hardness blocks. experimental procedure was designed using Taguchi Method. For this purpose the following factors were studied: austenitizing temperature, tempering condition, grinding condition, subzero treatment, lapping time, $15{\mu}m$ polishing time, final polishing time. These factors were processed and then ten hardness values were measured on each specimen. SN (signal to noise) ratio for each condition was calculated with standard variations of these values. Finally, from the calculated value of ANOVA on SN ratios, the lapping time was found to be the main factor Better uniformity with longer lapping time implies that residual stress that was formed after quenching is a dominent parameter that affects on the uniformity of hardness. Therefore, step-quenching method was adapted to minimize the residual stress. By this modification of quenching procedure, the hardness uniformity was improved remarkably and the yield ratio was increased from 55% to 88%.

• 한국표면공학회지
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• 제53권1호
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• pp.29-35
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• 2020

In this study, five different specimen preparation methods were introduced and their advantages and disadvantages were presented. One of them, an epoxy mounting method has advantages of constant exposure area, ease of surface preparation without touching the specimen surface during polishing or cleaning, use of small amount of material and ease of specimen reuse by polishing or etching. However, in order to eliminate unexpected errors resulting from preferable reaction at the specimen/epoxy interface and contact resistance between the specimen and copper conducting line for electrical connection, it is recommended to cover the wall side of the specimen with porous anodic oxide films and to remain the contact resistance lower than 1 ohm. The increased contact resistance between the specimen and Cu conducting line appeared to result in increases of anodizing voltage and solution temperature during anodizing by which thickness and hardness of anodizing film on Al2024 alloy were drastically decreased and color of the films became more brightened.

• 공학기술논문지
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• 제6권2호
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• pp.121-124
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• 2013

This paper proposed a new concept of estimating method for LED(light-emitting diode) delamination with high accuracy. Usually, The LED is composed several materials which are LED chips, gold wire, phosphor, epoxy resin, adhesive, reflector and lead frame. These different materials are usually delaminated in a trouble conditions which are huge temperature difference, hot and humid or mechanical shocked. When the components are delaminated, a luminance will be lost, moisture be absorbed easily and a thermal resistance be increased attendantly. As a conventional method to estimate a delamination of LEDs, a solution immersing method is usually used in a field of LED manufacturing companies or researching institutes. This method has an advantage of simplicity but it is only shown that the existence of delamination or not. In this paper, we have proposed an estimating method for LEDs delamination using the polishing and the electron microscope. New proposed method has shown the result of confirming delamination without destruction and enabled quantitative analysis for LED delamination.

• 대한치과보철학회지
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• 제35권1호
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• pp.31-42
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• 1997

This study was performed to investigate the surface roughness of the Cerec Vita Mark II polished by various polishing techniques, compare with that of the Vintage enamel porcelain glazed by high temperature glazing technique. All of the Cerec specimen were finished with sequential use of high speed diamond burs(grit 45, 30 and $15{\mu}m$). The groups were divided into 5 groups : Group I : Cerec Vita Mark II block specimens polished with Sof-lex discs. Group II : Cerce Vita Mark II block specimens polished with Two Striper MPS. Group III : Cerce Vita Mark II block specimens polished with Enhance. Group IV : Cerce Vita Mark II block specimens polished with Porcelain laminate polishing FG kit. Group V : Vintage enamel porcelain glazed by high temperature glazing Technique. Each group was consisted of 10 specimens. The surfaces produced were examined quantitatively using a laser specular reflectance machine(Perthen RM600-s, Feinpruf Perthen GmbH., Germany) and qualitatively under SEM(JSM-5400, JEOL, Japan). The Results were as follows : 1. The arithmetic mean roughness value(Ra) in groups 1, 2, 3 and 4 was higher than that of group5. There was statistically significant difference(P<0.05). 2. The arithmetic mean roughness value(Ra) decreased in the following orders : group 1, group 2, group 4, group 3 and there was no statistically significant difference between group 1 and group 2, group 3, and group 4. There was statistically significant difference among group 1, 2, and group 3, 4 and group 5(P<0.05). 3. The maximum individual peak-to-valley-height(Rmax) decreased in the following orders : group 2, group 1, group 4, group 3, group 5 and there was no statistically significant difference between group 1 and 2, group 1 and group 4, group 3 and group 5. There was statistically significant difference among group 1, 2, and group 1, 4 and group 3, 5(P<0.05). 4. The treated surfaces of group 5 had smoother surface than that of groups 1, 2, 3, 4 with SEM.

• 마이크로전자및패키징학회지
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• 제27권3호
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• pp.89-93
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• 2020

반도체 패키지의 경박단소화로 인해 발생하는 복잡한 휨 거동은 내부 응력을 발생시켜 박리나 균열과 같은 다양한 기계적인 결함을 야기한다. 이에 따른 수율 감소를 막기 위해 휨 거동을 정확하게 예측하려는 노력은 다양한 측면에서 그 접근이 이루어지고 있다. 이 중 패키지를 구성하는 주 재료인 실리콘 웨이퍼는 일반적으로 균질한 물질로 취급되어 열에 의한 휨 거동은 전혀 없는 것으로 묘사된다. 그러나 실리콘을 얇게 가공하기 위해서 진행되는 그라인딩과 폴리싱에 의해 상온에서 휨이 발생한다는 사실이 보고되어 있고, 이는 표면에 형성되는 damage layer가 두께 방향으로 불균질함을 발생시키는 것으로부터 기인한다. 이에 본 논문에서는 반도체 패키징 공정 중 최고온 공정 과정인 solder reflow 온도에서 단면 연마된 웨이퍼가 나타내는 휨 거동을 측정하고, 이러한 휨 량이 나타나는 원인을 연마된 면과 그렇지 않은 면의 열팽창계수를 측정함으로써 밝혀내었다. 측정에는 미세 변형률과 형상이 모두 측정 가능한 3차원 디지털 이미지 상관법(Digital Image Correlation; DIC)을 이용하였다.

• 한국표면공학회지
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• 제33권2호
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.