• The Journal of the Korea Contents Association
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• v.20 no.1
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• pp.392-402
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• 2020

Many modern movies and animations rely heavily on CG (computer graphics). The use of CG has made it possible to produce beyond the limits of visual expression. There has also been an increase in technical and artistic efforts to create new and high quality CGs. Look development is the process of modifying and creating shaders and renderings in 3D to produce CGI (computer-generated imagery) that meets the director's intentions. However, small production or projects may have relatively little or no awareness of look development in the production pipeline. The problems that can occur when look development is not preceded are classified into three categories. first, the shader may react differently under the same lighting conditions. Second, there can be a problem in communication between workers. Third, there is a waste of not promising a look for a given situation. As a way to avoid these problems I studied by creating consistency by the look development system. In the limitation that make it difficult for small studios to do look development because of small workers, time and cost, it is meaningful to study and present a simple look development process that can be carried out by individual or small production.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.2
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• pp.13-19
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• 2012

The techniques of 3d image processing have broadly used in the areas including movies, games, performances, exhibitions. In addition, increasing demands for practical uses have gradually extended to the areas of architecture, medicine, nuclear power plant. However, dominant techniques for 3d image processing seem to depend on multi-camera in which two stereo images are merged into one image. Also the pipeline has limitations to provide real-time 3d viewer in ubiquitous computing. It is not able to be applicable onto most general screens as well. In addition, the techniques can be utilized for the real-time 3d game play without a particular monitor or convertor. Hence, the research presented here is to aim at developing an efficient real-time 3d viewer using only mono camera which do not need post processing for editing as well.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.1-10
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• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.2 s.314
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• pp.1-10
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• 2007

Branch prediction accuracy is critical for the overall system performance. Branch miss-prediction penalty is the one of the significant performance limiters for improving processor performance, as the pipeline deepens and the instruction issued per cycle increases. In this paper, we propose "Dynamic Per-Branch History Length Fitting Method" by tracking the data dependencies among the register writing instructions. The proposed solution first identifies the key branches, and then it selectively uses the histories of the key branches. To support this mechanism, we provide a history length adjustment algorithm and a required hardware module. As the result of simulation, the proposed mechanism outperforms the previous fixed static method, up to 5.96% in prediction accuracy. Furthermore, our method introduces the performance improvement, compared to the profiled results which are generally considered as the optimal ones.

• Corrosion Science and Technology
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• v.19 no.3
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• pp.122-130
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• 2020

In this study, a corrosion failure analysis of a heat transport pipe was conducted, as the result of a pinhole leak. Interestingly, the corrosion damage occurred externally in the pipeline, resulting in severe thickness reduction near the seam line. Also, while a stable magnetite protective film formed on the inner surface, the manganese oxide formation occurred only on the outer surface. The interior and exterior of the pipe were composed of ferrite and pearlite. The large manganese sulfide and alumina inclusions were found near the seam line. In addition, the manganese sulfide inclusions resulted in grooving corrosion, which progressed in the seam line leading to the reduction in the thickness, followed by the exposure of the alumina in the matrix to the outer surface. To note, the corrosion was accelerated by pits generated from the boundaries separating the inclusions from the matrix, which resulted in pinhole leaks and water loss.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.452-459
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• 2020

The electric actuator receives the user's command input signal (open/closed/stop), checks the status of various sensors (valve position, rotational force, motor status, etc.)in the actuator, and controls the motor forward/reverse to open and close the valve. It is a device that outputs the current state of an actuator (valve) and is used in various fields such as dams, power plants, water and sewage facilities, and oil pipeline facilities. If an electric actuator is installed in a power plant and a problem occurs during operation, it can cause a large economic loss, so system reliability is vert important. In this study, in order to increase the safety of the electric actuator, the development of an electric actuator control device capable of setting the ON/OFF time in hardware was conducted to solve the reliability problem that may occur in software. In addition, the electric actuator control device development environment was developed using Xilinx's Spartan7 FPGA and Altium tool.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.9
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• pp.1103-1108
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• 2012

A main steam pipe system is a branch pipe that connects a boiler with a turbine. Water hammering analysis is very important for limiting the damage caused to pipe systems by operation conditions. Water hammering created by an unsteady flow in pipeline systems can cause excessive change in pressure, vibration, and noise. The main steam pipe structure should be designed to safely maintain the pressure pulsation and several vibrations under operation environments. This study evaluated the structural integrity of a main steam pipe during suspended and normal operation by using the ASME fatigue life methodology and finite element analysis. In the analysis, water hammering was used for transient analysis. The calculated alternating stress and fatigue stress were compared with the applicable limits of ASME fatigue life. All the evaluation results satisfied the requirements of the ASME fatigue life.

• Journal of the Korean Society for Nondestructive Testing
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• v.21 no.1
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• pp.32-38
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• 2001

Although the ultrasonic method has been developed and used widely in the fields, it has been used only for measuring the defect size and thickness loss. In this study, the relationship between surface wave attenuation through micro-crack growth and variation of velocity under repeated cyclic loading has been investigated. The specimens are adopted from 2.25Cr-1Mo steel, which is used for power plant and pipeline system, and have dimensions of $200{\times}40{\times}4mm$. The results of ultrasonic test with a 5MHz transducer show that surface wave velocity gradually decreases from the point of 60% of fatigue life and the crack length of 2mm with the increasing fatigue cycles. From the results of this study, it is found that the technique using the ultrasonic velocity change is one of very useful methods to evaluate the fatigue life nondestructively.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.7
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• pp.847-862
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• 1999

본 논문에서는 유한버퍼의(finite-buffered) 동기화된(synchronous) 큐잉모델(queueing model)을 이용하여 명령어들간의 병렬성, 분기명령의 빈도수, 분기예측(branch prediction)의 정확도, 캐쉬미스 등의 파라미터들을 고려하여 프로세서의 명령어 실행율을 예측하며 캐쉬의 성능과 파이프라인 성능간의 관계를 분석할 수 있는 새로운 해석적 모델을 제안하였다. 해석적 모델은 모델의 타당성을 검증하기 위해서 시뮬레이션을 수행하여 얻은 결과와 비교하였다. 해석적 모델과 시뮬레이션을 비교한 결과 대부분 10% 오차 내에서 일치하였다. 본 연구를 통하여 얻은 해석적 모델을 사용하면 시뮬레이션에서는 드러나지 않는 성능제약의 원인에 대한 명확한 규명이 가능하기 때문에 성능향상을 위한 설계자료를 얻을 수 있으며, 시스템 성능 밸런스를 위한 캐쉬와 비순차이슈 파이프라인 성능간의 관계에 대한 정확한 분석이 가능하다.Abstract This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc.. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error compared to simulation results. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.