• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.24-31
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• 1998

This paper presents a pipeline high-level synthesis tool for designing trace-back systolic array viterbi decoder. It consists of a dta flow graph(DFG) generator and a pipeline data path synthesis tool. First, the DFG of the vitrebi decoder is generated in the from of VHDL netlist. The inputs to the DFG generator are parameters of the convolution encoder. Next, the pipeline scheduling and allocationare performed. The synthesis tool explores the design space efficiently, synthesizes various designs which meet the given constraints, and choose the best one.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.149-158
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• 1994

Through high level synthesis, designers can obtain the precious information on the area and speed trade-offs as well as synthesized datapaths from behavioral design descriptions. While previous researches were concentrated on the synthesis of pipelined, datapaths with fixed DII (Data Initiation Interval) by inserting delay elements where needed, we propose a novel methodology of synthesizing pipeline structures with variable DIIs. Determining the time-overlapping of pipeline stages with variable DIIs, the proosed algorithm performs scheduling and module allocation using the time-overlapping information. Experimental results show that significant improvement can be achieved both in speed and in area.

• Journal of the Korean Society of Industry Convergence
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• v.3 no.4
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• pp.299-306
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• 2000

이 논문은 파이프라인 함성을 위한 상위수준 데이터 경로 하성과 콘트롤 합성의 통합에 관한 연구이다. 현재 대부분의 상위수준 합성 방법은 콘트롤 영역의 영향을 무시하는데 보다 나은 설계를 위하여 데이터 경로디자인 영역과 콘트롤 디자인 영역을 통합하여 탐색하는 파이프라인 상위수준함성 도구를 구현했다. 이 도구는 비용 제한 하에서 최고 성능의 파이프라인을 합성하는 비용재한합성과 성능 제한 하에서 최서 비용의 파이프라인을 합성하는 성능 제한합성의 두 가지 방식을 제공한다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.53-67
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• 1994

This paper describes the design of a high-level synthesis system. SODAS-VP. which automatically generates hardwares executing operation sequences in pipelined fashion.Target architecture and clocking schemes to drive pipelined datapath are determined, and the handling of pipeline hazards which degrade the performance of pipeline is considered. Partitioning of an operation into load, operation, and store stages, each of which is executed in partitiones control step, is performend. Pipelinecl hardware is generated by handling pipeline hazards with internal forwarding or delay insertion techniques in partitioning process and resolving resource conflicts among the partitioned control steps with similarity measure as a priority function in module allocation process. Experimental results show that SODAS-VP generates hardwares that execute faster than those generated by HAL and ALPS systems. SODAS-VP brings improvement in execution speed by 17.1% and 7.4% comparing with HAL and ALPS systems for a MCNC benchmark program, 5th order elliptical wave filter,respectively.

• Journal of IKEEE
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• v.14 no.4
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• pp.270-276
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• 2010

In this paper, performance comparison of FFT algorithms for OFDM system is shown and advantage of proposed SRFFT is verified through implementation. For the single input and output structure in the most OFDM communication systems, adaptation of SRFFT might be inefficient. In this paper, improved SRFFT with pipeline structured FFT/IFFT of single input and output is developed and verified with Matlab, VHDL, synthesis tool and simulation tool.

• The Journal of the Korea Contents Association
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• v.8 no.7
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• pp.128-134
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• 2008

On-line game industry had accomplished much growths and development When manufacture game adaptively and easily game manufacture pipeline and fast manufacture schedule that is shorted according to special quality of on-line by one of pain of game companies, application need manufacture pipe line Wish to collect existing manufacture process and pipeline connection research and collect existing spot manufacture pipeline through present office specialist, analyze synthesis and draw game manufacture element and manufacture pipeline in this research. Analyze pipeline of that research progress process is overview and on-line game arcade game Mobile crab collection and progressed pipeline that is optimized by this by period of ten days that draw conclusion after deduction.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.49-56
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• 2010

In this paper, a low-power frequency offset synchronization structure using CORDIC algorithm is proposed. Main blocks of frequency offset synchronization are estimation and compensation block. In the proposed frequency offset estimation block, implementation area is reduced by using sequential CORDIC, and throughput is accelerated by using 2 step CORDIC. In the proposed frequency offset compensation block, pipeline CORDIC is utilized for area reduction and high speed processing. Through MatLab simulation, function for proposed structure is verified. Proposed frequency offset synchronization structure is implemented by Verilog-HDL coding and implementation area is estimated by Synopsys logic synthesis tool.

• Smart Media Journal
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• v.4 no.4
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• pp.39-46
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• 2015

This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.

• Structural Engineering and Mechanics
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• v.84 no.6
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• pp.733-741
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• 2022

The amount of natural gas that is used on a worldwide scale is continuously going up. Natural gas and acidic components, such as hydrogen sulfide and carbon dioxide, cause significant corrosion damage to transmission lines and equipment in various quantities. One of the fundamental processes in natural gas processing is the separation of acid gases, among which the safety and environmental needs due to the high toxicity of hydrogen sulfide and also to prevent wear and corrosion of pipelines and gas transmission and distribution equipment, the necessity of sulfide separation Hydrogen is more essential than carbon dioxide and other compounds. Given this problem's significance, this endeavor aims to extend the lifespan of the transmission lines' pipes for gas and oil. Zinc oxide nanoparticles made from the environmentally friendly source of Allium scabriscapum have been employed to accomplish this crucial purpose. This is a simple, safe and cheap synthesis method compared to other methods, especially chemical methods. The formation of zinc oxide nanoparticles was shown by forming an absorption peak at a wavelength of about 355 nm using a spectrophotometric device and an X-ray diffraction pattern. The size and morphology of synthesized nanoparticles were determined by scanning and transmission electron microscope, and the range of size changes of nanoparticles was determined by dynamic light scattering device.