• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.102-105
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.5
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• pp.24-29
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• 1976

In the phase locked AM signal detection, phase locked loop is used to extract a synchronous carrier from an input AM signal. Under the assumption that input noise is white Gaussian and free-running frequency of voltage controlled oscillator is the same that of an input carrier, operational behaviours of phase locked loop is analyzed and signal to noise ratio of the detection is derived quentitatively. The results show that the phase locked AM signal detection method offers a higher degree of noise mmunity than conventional AM signal detections.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Current Optics and Photonics
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• v.7 no.5
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• pp.557-561
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• 2023

Ultralow-noise soliton pulse generation over a wider Fourier frequency range is highly desirable for many high-precision applications. Here, we realize a low-phase-noise soliton pulse generation by transferring the low phase noise of a mode-locked laser to a silica microcomb. A 21.956-GHz and a 9.9167-GHz Kerr soliton combs are synchronized to a 2-GHz and a 2.5-GHz mode-locked laser through a fractional optoelectronic phase-locked loop, respectively. The phase noise of the microcomb was suppressed by up to ~40 dB at 1-Hz Fourier frequency. This result provides a simple method for low-phase-noise soliton pulse generation, thereby facilitating extensive applications.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.605-615
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• 1986

The phase-locked loop(PLL) is a communication receiver which operates as a coherent detector by continuously correcting the phase error. In this paper analysis for the Phase-error behavior of analog phase-locked loop (APLL) in the presence of additive white gaussian noise has been done theoretically and experimentally. A close form solution of the first-order loop is obtained and approximate solutions are derived for the second-order loops with RC, leadlag and perfect integrator filters. The perdormance of APLL's and their characteristics are also thoroughly investigated through experiments. In order to analyze the effect of the stochastic nature on nonlinear dynamics characteristics of the second order APLL, the phase error distribution and its variance have been obtained by using the Fokker-Planck equation. Theoretical results agree closely with those of experiment.