• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.684_685
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• 2009

A digital sampling algorithm that uses a two high resolution integrating Voltmeters which are synchronized by Phase Lock Loop (PLL) time clock for accurately measuring the parameters, active and reactive power, for sinusoidal power measurements is presented. The PLL technique provides high precision measurements, root mean square (rms), phase and complex voltage ratio, of the AC signal. The system has been designed to be used at the Korean Research Institute of Standards and Science (KRISS) as a reference power standard for electrical power calibrations. The test results have shown that the accuracy of the measurements is better than $10 {\mu}W/VA$ and the level of uncertainty is valid for the power factor range zero to 1 for both lead and lag conditions. The system is fully automated and allows power measurements and calibration of high precision wattmeters and power calibrators at the main power frequencies 50 and 60 Hz.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.268-269
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• 2017

This paper presents an improved current control strategy for a three-phase grid-connected inverter under distorted grid conditions. Distorted grid condition is undesirable due to negative effects such as power losses and heating problem in electrical equipments. To enhance the power quality of distributed generation systems under such a condition, a modulated finite control set - model predictive control (MFCS-MPC) scheme will be proposed, in which the optimal switching signals of inverter are chosen by online basis using the principle of current error minimization. In addition, the moving average filter (MAF) is used to improve the phase-lock loop in order to obtain the harmonic-free reference currents on the stationary frame. The usefulness of the proposed MFCS-MPC method is proved by the comparative simulation results under different operating conditions.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.95-96
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• 2015

본 논문에서는 왜곡된 전원 전압과 주파수 변동 하에서도 입력 전류를 정현적으로 제어하도록 하는 단상 PWM 컨버터의 동기좌표계 전류 제어 기법을 제안한다. 왜곡된 전원 전압은 PWM 컨버터 제어를 위한 제어 위상각을 왜곡시켜 입력 전류에 고조파를 발생시키며, 전원 주파수의 변동 역시 입력 전류의 제어 성능을 저하시킨다. 본 논문에서는 위상각의 왜곡 성분을 이용하여 지령 전류를 보상하고 동기좌표계 PLL (Phase Lock Loop) 제어기의 출력으로부터 주파수 변동분을 검출하여 왜곡된 전원 전압과 주파수하에서도 정현적인 전류 제어가 가능하도록 하였다. 제안된 기법의 유용성은 실험을 통해 확인하였다.

• Annual Conference of KIPS
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• 2010.11a
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• pp.629-632
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• 2010

본 논문에서는 Fringe Pattern profilometry(FPP)을 이용한 높이 측정 시스템을 구현하고, R, G, B 각 컬러 채널별로 위상이 다른 파형을 인가함으로써 Phase shifting 방법을 이용한 실시간 위상 정보를 획득할 수 있게 한다. 디지털 프로젝터의 비선형성으로 인해 필연적으로 발생하는 하모닉스 성분을 근사화된 정현파를 인가함으로써 높이 정보에서 가장 큰 문제를 발생하는 2차 하모닉스 성분을 줄인다. 이렇게 구한 위상 값을 Digital Phase Loop Lock(DPLL)회로에 인가함으로써 3차원 모양 정보를 실시간으로 획득 가능하게 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.899-905
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• 2017

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.61-67
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• 2009

This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.112-119
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• 2009

This paper presents a PLL(Phase Lock Loop) approach for effective speed and torque control of high speed miniature BLDCM(Brushless DC Motor) using hall sensor. The proposed speed control method based on PLL uses only a phase shift between reference pulse signal according to speed reference and actual pulse signal from hall sensor. It doesn't use any speed calculation, and calculates a direct current reference from phase shift. The current reference is changed to reduce the phase shift between reference and actual pulse. So the actual speed can keep the reference speed. The proposed control scheme is very simple but effective speed control is possible. In order to obtain a smooth torque production, the reference current is changed using acceleration and deceleration slope. The proposed control scheme is verified by experimental results of the 50W, 40,000[rpm] high speed miniature BLDCM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.