• Communications for Statistical Applications and Methods
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• v.31 no.5
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• pp.601-612
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• 2024

A functional clustering analysis is a crucial machine learning technique in functional data analysis. Many functional clustering methods have been developed to enhance clustering performance. Moreover, due to the phase variability between functions, elastic functional clustering methods, such as applying the Fisher-Rao metric, which can manage phase variation during clustering, have been developed to improve model performance. However, aligning functions without considering the phase variation can distort functional information because phase variation can be a natural characteristic of functions. Hence, we propose a state-of-the-art functional hierarchical clustering that can manage phase and amplitude variations of functional data. This approach is based on the phase and amplitude separation method using the norm-preserving time warping of functions. Due to its invariance property, this representation provides robust variability for phase and amplitude components of functions and improves clustering performance compared to conventional functional hierarchical clustering models. We demonstrate this framework using simulated and real data.

• ETRI Journal
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• v.25 no.1
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• pp.19-24
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• 2003

This paper describes the performance of a Ku-band 5-bit monolithic phase shifter with metal semiconductor field effect transistor (MESFET) switches and the implementation of a ceramic packaged phase shifter for phase array antennas. Using compensation resistors reduced the insertion loss variation of the phase shifter. Measurement of the 5-bit phase shifter with a monolithic microwave integrated circuit demonstrated a phase error of less than $7.5{\circ}$ root-mean-square (RMS) and an insertion loss variation of less than 0.9 dB RMS for 13 to 15 GHz. For all 32 states of the developed 5-bit phase shifter, the insertion losses were $8.2{\pm}1.4$dB, the input return losses were higher than 7.7 dB, and the output return losses were higher than 6.8 dB for 13 to 15 GHz. The chip size of the 5- bit monolithic phase shifter with a digital circuit for controlling all five bits was 2.35 mm ${\times}$1.65 mm. The packaged phase shifter demonstrated a phase error of less than $11.3{\circ}$ RMS, measured insertion losses of 12.2 ${\pm}$2.2 dB, and an insertion loss variation of 1.0 dB RMS for 13 to 15 GHz. For all 32 states, the input return losses were higher than 5.0 dB and the output return losses were higher than 6.2 dB for 13 to 15 GHz. The size of the packaged phase shifter was 7.20 mm${\times}$ 6.20 mm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.3
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• pp.371-375
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• 2014

In this paper, we compared the performances of the Right Handed Transmission Line (RHTL) and the Left Handed Transmission Line (LHTL) phase shifters as a frequency translator. Unlike other phase shifters, both phase shifters show a $0^{\circ}-360^{\circ}$ phase variation for a broadband frequency and compact in size which are ideal to use as a frequency translator. For the performance comparison, we fabricated both a RHTL and a LHTL phase shifter to cover 1.5 GHz - 2.4 GHz range with the whole $360^{\circ}$ phase variation. For the frequency range, a LHTL based frequency translator showed a much better performance whose Spurious Free Dynamic Range (SFDR) is 4dB - 17dB higher than the RHTL based frequency translator when the sawtooth modulation freqncy is 11 kHz. This is due to the linear phase-voltage variation of LHTL phase shifter. Furthermore, the LHTL phase shifter shows a less insertion loss and a insertion loss variation than the RHTL phase shifter. Overall, the LHTL based frequency translator outperformed RHTL based freqency translator.

• Journal of Astronomy and Space Sciences
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• v.35 no.4
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• pp.219-225
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• 2018

Cosmic rays are ions that move at relativistic speeds. They generate secondary cosmic rays by successive collisions with atmospheric particles, and then, the secondary particles reach the ground. The secondary particles are mainly neutrons and muons, and the neutrons are observed by the ground neutron monitor. This study compared the diurnal variation in cosmic ray intensity obtained via harmonic analysis and that obtained through the pile-up method, which was examined in a previous study. In addition, we analyzed the maximum phase of the diurnal variation using four neutron monitors with a cutoff rigidity below approximately 6 GV, located at similar longitudes to the Oulu and Rome neutron monitors. Expanding the data of solar cycles 20-24, we examined the time of the maximum cosmic ray intensity, that is, the maximum phase regarding the solar cyclic modulation. During solar cycles 20-24, the maximum phase derived by harmonic analysis showed no significant difference with that derived by the pile-up method. Thus, the pile-up method, a relatively straightforward process to analyze diurnal variation, could replace the complex harmonic analysis. In addition, the maximum phase at six neutron monitors shows the 22-year cyclic variation very clearly. The maximum phase tends to appear earlier and increase the width of the variation in solar cycles as the cutoff rigidity increases.

• Journal of the Korean Ceramic Society
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• v.30 no.5
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• pp.365-372
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• 1993

Variation of dielectric constant in PMN-Pyrochlore diphasic mixtures were investigated with grain size of pyrochlore phase. Size of pyrochlore phase was controlled by the numbers of calcining and sedimentation method during powder processing. When grain size of pyrochlore phase is large in the sintered specimen, dielectric constant slowly decreased with increase of amount of pyrochlore phase. On the contary, grain size of pyrochlore phase is small, dielectric constant drastically decreased. It was thought that small sized pyrochlore grains more easily surrounded high dielectric phase (perovskite PMN) than large ones with addition of pyrochlore phase.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.867-873
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• 1988

The degradation due to channel distortion in a quadrature modulation system from the ideal constant values over the bandwidth of a direct sequence spread spectrum signal are considered. Through using series expansion for the channel gain and phase response, the degradation in the correlator output at the receiver is found as a function of the parameters involved , including phase error, delay error, linear gin variation, quadratic gain variation, and quadratic phase variation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1376-1385
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• 2000

The phase characteristic of delay line in feedfarward linearizer has been changed due to variation of operating temperature. In this paper, design method of fixed phase control circuit of group delay line using adaptive vector control is derived. To maintain transfer characteristics of nominal operating temperature, the error correlated signals, which are changed adaptively due to changing of temperature, are added to main signals. The proposed method maintains transfer characteristics under 0.06dB of insertion loss and 0.36$^{\circ}$ of phase variation in case of 1-tone(880 MHz) and under 0.07 dB of insertion loss and 0.35$^{\circ}$ of phase variation in case of 2-tones(877 MHz, 882 MHz) for 10dB input power dynamic range and +/-10$^{\circ}$ phase variation respectively.

• Journal of Power Electronics
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• v.16 no.1
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

• Journal of the Semiconductor & Display Technology
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• v.14 no.4
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• pp.72-77
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• 2015

Three-level diode clamped multilevel inverter, generally known as neutral point clamped (NPC) inverter, has an inherent problem causing neutral point (NP) potential variation. Until now, the NP potential problem of variation has been investigated and lots of solutions have also been proposed. This paper presents a neutral point voltage control technology using the anti-windup PI controller and offset technology of PWM (Pulse Width Modulation) to control the variation of NPC 3-phase three-level inverter neutral point voltage. And the proposed algorithm is tested and verified using a PLL (Phase Locked Loop) in order to synchronize the phase voltage from the line voltage of grid. It significantly improves the voltage balancing under a solar fluctuation conditions of the inverter. Experimental results show the good performance and effectiveness of the proposed method.