• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• 대한임베디드공학회논문지
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• 제11권2호
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• pp.107-116
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• 2016

Density of Phase-Change Memory (PCM) devices has been doubled through the employment of multi-level cell (MLC) technology. However, this doubled-capacity comes in the expense of severe performance degradation, as compared to the conventional single-level cell (SLC) PCM. This negative effect on the performance of the MLC PCM detracts from the potential benefits of the MLC PCM. This paper introduces an efficient way of minimizing the performance degradation while maximizing the capacity benefits of the MLC PCM. To this end, we propose a location-aware hybrid management of SLC and MLC in compressed PCM main memory systems. Our trace-driven simulations using real application workloads demonstrate that the proposed technique enhances the performance and energy consumption by 45.1% and 46.5%, respectively, on the average, over the conventional technique that only uses a MLC PCM.

• 정보과학회 논문지
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• 제42권9호
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• pp.1071-1077
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• 2015

본 논문은 PCM을 가상메모리 스왑 장치로 사용하는 시스템을 위한 새로운 페이지 교체 기법을 제안한다. 제안하는 기법은 메모리 내의 각 페이지에 대한 수정 정도를 고려해서 교체 대상 페이지를 선정하며 이를 통해 PCM에 발생시키는 쓰기량을 줄인다. 즉, 제안하는 기법은 페이지의 수정 정도를 서브페이지 단위로 관리하고 최근에 사용되지 않은 페이지 중 수정된 서브페이지의 수가 최소인 페이지를 교체한다. 트레이스를 이용한 재현 실험을 통해 제안한 기법이 기존 CLOCK 알고리즘 대비 평균 22.9% 최대 73.7%의 PCM 쓰기량을 절감함을 확인하였다. 또한 PCM의 수명과 에너지 소모율을 각각 평균 49.0%와 3.0% 개선함을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• Applied Science and Convergence Technology
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• 제23권1호
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• pp.34-39
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• 2014

The programmable switches which control the delivery of electrical signals in programmable logic devices are fabricated using memory technology. Although phase change memory (PCM) technology is one of the most promising candidates for the manufacturing of the programmable switches, the threshold switching material should be added to a PCM cell for realization of the programmable switches based on PCM technology. In this work, we report the impurity-doped $Ge_2Sb_2Te_5$ (GST) chalcogenide alloy exhibiting threshold switching property. Unlike the GST thin film, the doped GST thin film prepared by the incorporation of In and P into GST is not crystallized even at the postannealing temperature higher than $200^{\circ}C$. This specific crystallization behavior in the doped GST thin film is attributed to the stabilization of the amorphous phase of GST by In and P doping.

• 한국진공학회지
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• 제19권2호
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• pp.155-160
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• 2010

상변화 메모리 소자 제작 공정의 단위 스텝인 최종 열처리의 온도가 상변화 메모리 소자 특성에 미치는 영향을 고찰하였다. $Ge_2Sb_2Te_5$ (GST) 박막을 활성 물질로 하는 기공(pore) 구조의 단위 상변화 메모리 소자를 제작하고, $160^{\circ}C$에서 $300^{\circ}C$까지의 온도 범위에서 최종 열처리를 실시하였다. 상변화 메모리 소자의 SET 저항에서 RESET 저항으로의 셀 저항 변화 양상은 최종 열처리 온도에 따라 큰 차이를 나타내었다. 정상적인 상변화 메모리 동작 특성을 얻을 수 있는 임계 열처리 온도가 존재하며, 열처리 온도가 그 온도에 비해 상대적으로 높거나 낮은 경우에는 소자가 오동작하거나 불안정하게 동작하는 것을 확인하였다. 이러한 열처리 온도의 효과는 열에너지에 따른 상부전극-GST 박막-발열층 다층 구조의 열적 안정성과 밀접한 관련이 있는 것으로 보인다.

• 한국인터넷방송통신학회논문지
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• 제21권2호
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• pp.27-32
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• 2021

본 논문은 차세대 사물인터넷 디바이스를 위한 에너지 효율적인 캐시 및 메모리 관리 기법을 제안한다. 제안하는 기법은 전력 소모가 적은 상변화 메모리를 사물인터넷 디바이스의 메인 메모리로 채택하고 캐시 메모리의 관리 시 쓰기 연산에 취약한 상변화 메모리의 쓰기량을 최소화하는 방향으로 설계한다. 구체적으로 살펴보면 최종단 캐시 메모리에서 캐시 블록이 삭제되어 메인 메모리로 반영될 때, 캐시 블록을 구성하는 캐시 라인별 수정 여부를 추적하여 상변화 메모리에 쓰기 발생량을 적게 발생시키는 캐시 블록을 우선적으로 교체한다. 또한, 최종단 캐시 메모리에서 캐시 블록의 참조 비트와 캐시 라인의 수정 비트를 함께 고려함으로써 메모리 시스템의 성능은 훼손하지 않으면서 에너지 소모를 줄이는 방식을 사용한다. 스펙 벤치마크를 이용한 시뮬레이션 실험을 통해 제안한 기법이 상변화 메모리에 발생하는 쓰기량을 평균 34.6% 줄이고 전력 소모를 28.9% 줄이면서 메모리의 성능 저하는 발생시키지 않음을 보인다.

• 한국전기전자재료학회논문지
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• 제32권6호
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• pp.448-453
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• 2019

This work reports the electrical characteristics of and temperature distribution in chalcogenide phase change memory (PCM) devices that have a self-aligned structure. GST (Ge-Sb-Te) chalcogenide alloy films were formed in a self-aligned manner by interdiffusion between sputter-deposited Ge and $Sb_2Te_3$ films during thermal annealing. A transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis demonstrated that the local composition of the GST alloy differed significantly and that a $Ge_2Sb_2Te_5$ intermediate layer was formed near the $Ge/Sb_2Te_3$ interface. The programming current and threshold switching voltage of the PCM device were much smaller than those of a control device; this implies that a phase transition occurred only in the $Ge_2Sb_2Te_5$ intermediate layer and not in the entire thickness of the GST alloy. It was confirmed by computer simulation, that the localized phase transition and heat loss suppression of the GST alloy promoted a temperature rise in the PCM device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.80-81
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a sample of PRAM with thermal protected layer. We have investigated the phase transition behaviors in function of process factor including thermal protect layer. As a result, we have observed that set voltage and duration of protect layer are more improved than no protect layer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.222.2-222.2
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• 2015

A $Ge_2Sb_2Te_5$ nanowire (GST NW) phase change memory device is investigated with Joule heating electrodes. GST is the most promising phase change materials, thus has been studied for decades but atomic structure transition in the phase-change area of single crystalline phase-change material has not been clearly investigated. We fabricated a phase change memory (PCM) device consisting of GST NWs connected with WN electrodes. The GST NW has switching performance with the reset/set resistance ratio above $10^3$. We directly observed the changes in atomic structure between the ordered hexagonal close packed (HCP) structure and disordered amorphous phase of a reset-stop GST NW with cross-sectional STEM analysis. Amorphous areas are detected at the center of NW and side areas adjacent to heating electrodes. Direct imaging of phase change area verified the atomic structure transition from the migration and disordering of Ge and Sb atoms. Even with the repeated phase transitions, periodic arrangement of Te atoms is not significantly changed, thus acting as a template for recrystallization. This result provides a novel understanding on the phase-change mechanism in single crystalline phase-change materials.