• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.6
• /
• pp.741-749
• /
• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.2
• /
• pp.107-116
• /
• 2016

Density of Phase-Change Memory (PCM) devices has been doubled through the employment of multi-level cell (MLC) technology. However, this doubled-capacity comes in the expense of severe performance degradation, as compared to the conventional single-level cell (SLC) PCM. This negative effect on the performance of the MLC PCM detracts from the potential benefits of the MLC PCM. This paper introduces an efficient way of minimizing the performance degradation while maximizing the capacity benefits of the MLC PCM. To this end, we propose a location-aware hybrid management of SLC and MLC in compressed PCM main memory systems. Our trace-driven simulations using real application workloads demonstrate that the proposed technique enhances the performance and energy consumption by 45.1% and 46.5%, respectively, on the average, over the conventional technique that only uses a MLC PCM.

• Journal of KIISE
• /
• v.42 no.9
• /
• pp.1071-1077
• /
• 2015

In this paper, we adopt PCM (phase-change memory) as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among the pages not recently used. Experimental results show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.1
• /
• pp.68-76
• /
• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• Applied Science and Convergence Technology
• /
• v.23 no.1
• /
• pp.34-39
• /
• 2014

The programmable switches which control the delivery of electrical signals in programmable logic devices are fabricated using memory technology. Although phase change memory (PCM) technology is one of the most promising candidates for the manufacturing of the programmable switches, the threshold switching material should be added to a PCM cell for realization of the programmable switches based on PCM technology. In this work, we report the impurity-doped $Ge_2Sb_2Te_5$ (GST) chalcogenide alloy exhibiting threshold switching property. Unlike the GST thin film, the doped GST thin film prepared by the incorporation of In and P into GST is not crystallized even at the postannealing temperature higher than $200^{\circ}C$. This specific crystallization behavior in the doped GST thin film is attributed to the stabilization of the amorphous phase of GST by In and P doping.

• Journal of the Korean Vacuum Society
• /
• v.19 no.2
• /
• pp.155-160
• /
• 2010

The effect of process temperature of a final annealing step in the fabrication of phase change memory (PCM) devices was investigated. Discrete PCM devices employing $Ge_2Sb_2Te_5$ (GST) films as an active element were made in a pore-style configuration, and they were annealed at various temperatures ranging from 160 to $300^{\circ}C$. The behaviors of cell resistance change from SET resistance to RESET resistance were totally different according to the annealing temperatures. There was a critical annealing temperature for the fabrication of normal PCM devices and abnormal operations were observed in some devices annealed at temperatures lower or higher than the critical temperature. Those influences of annealing temperature seem closely related to the thermal stability of a top electrode/GST/heating layer multilayer structure in the PCM devices.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.2
• /
• pp.27-32
• /
• 2021

This paper proposes an energy-efficient cache and memory management scheme for next-generation IoT devices. The proposed scheme adopts a low-power phase-change memory (PCM) as the main memory of IoT devices, aims at minimizing the write traffic to PCM, which is vulnerable to write operations. Specifically, when a cache block of the last-level cache memory is flushed to main memory, the cache block that causes less writes to PCM is preferentially replaced by tracking the modifications of each cache line that constitutes the cache block. In addition, by considering the reference bit of the cache block and the dirty bit of the cache lines, our scheme reduces the energy consumption without degrading the memory system performances. Through simulations using SPEC benchmarks, it is shown that the proposed scheme reduces the write traffic to PCM by 34.6% on average and the power consumption by 28.9%, without memory performance degradations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.32 no.6
• /
• pp.448-453
• /
• 2019

This work reports the electrical characteristics of and temperature distribution in chalcogenide phase change memory (PCM) devices that have a self-aligned structure. GST (Ge-Sb-Te) chalcogenide alloy films were formed in a self-aligned manner by interdiffusion between sputter-deposited Ge and $Sb_2Te_3$ films during thermal annealing. A transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis demonstrated that the local composition of the GST alloy differed significantly and that a $Ge_2Sb_2Te_5$ intermediate layer was formed near the $Ge/Sb_2Te_3$ interface. The programming current and threshold switching voltage of the PCM device were much smaller than those of a control device; this implies that a phase transition occurred only in the $Ge_2Sb_2Te_5$ intermediate layer and not in the entire thickness of the GST alloy. It was confirmed by computer simulation, that the localized phase transition and heat loss suppression of the GST alloy promoted a temperature rise in the PCM device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.11a
• /
• pp.80-81
• /
• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a sample of PRAM with thermal protected layer. We have investigated the phase transition behaviors in function of process factor including thermal protect layer. As a result, we have observed that set voltage and duration of protect layer are more improved than no protect layer.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.222.2-222.2
• /
• 2015

A $Ge_2Sb_2Te_5$ nanowire (GST NW) phase change memory device is investigated with Joule heating electrodes. GST is the most promising phase change materials, thus has been studied for decades but atomic structure transition in the phase-change area of single crystalline phase-change material has not been clearly investigated. We fabricated a phase change memory (PCM) device consisting of GST NWs connected with WN electrodes. The GST NW has switching performance with the reset/set resistance ratio above $10^3$. We directly observed the changes in atomic structure between the ordered hexagonal close packed (HCP) structure and disordered amorphous phase of a reset-stop GST NW with cross-sectional STEM analysis. Amorphous areas are detected at the center of NW and side areas adjacent to heating electrodes. Direct imaging of phase change area verified the atomic structure transition from the migration and disordering of Ge and Sb atoms. Even with the repeated phase transitions, periodic arrangement of Te atoms is not significantly changed, thus acting as a template for recrystallization. This result provides a novel understanding on the phase-change mechanism in single crystalline phase-change materials.