• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.243-247
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• 1998

SO(Synchronous Oscillator)는 동기, 동조, 필터, 증폭, 분주를 하나의 과정으로 처리할 수 있는 회로망이며, CPSO(Coherent Phase Synchronous Oscillator)는 50에 2개의 외부 루프를 첨가함으로서 구성되며, SO의 모든 장점을 유지하면서 동조범위 안에서 위상차가 없는 것이 큰 특징이다. 본 논문에서는 CPSO의 이러한 성질을 이용하여 GPS (Global Positioning System)에서 많이 사용하고 있는 부호동기방식인 DLL(Delay Lock Loop)과 TDL(Tau dither Loop)을 대치할 수 있는, 회로가 간단하고 추적범위가 넓으며 동기가 용이한 CPSO를 GPS의 부호동기 시스템에 적용하였다.

• The Bulletin of The Korean Astronomical Society
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• v.31 no.2
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• pp.35.1-35.1
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• 2006

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.21-26
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• 2005

10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

• Journal of Yeungnam Medical Science
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• v.6 no.2
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• pp.217-222
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• 1989

In this study, high frequency oscillatory ventilator was designed and constructed. Using designed by phase-lock loop system, in order to accurately and easily treat both the outlet volume and rpm. A system has been designed and is being evaluated using CD4046A PLL IC. We use this PLL IC for the purpose of motor controls. The device consists of PLL system, pumping mechanism, piston, cylinder, and special crank shaft are required. This system characteristics were as follows : 1) Frequency : 20-1800rpm. 2) Outlet air volume : 1-50cc.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.333-339
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• 2012

Global flow of communication is a trend of high speed, digitalization, and high-capacity. Furthermore, spread spectrum method has been dominantly utilized to efficiently use the frequency which is the scarce resource. The PLL (Phase Lock Loop) which is a widely used frequency synthesizer in communication systems has few problems such as status interferences and hence, this study utilized the DDS (Direct Digital Synthesis) which is a digital device that can minimize the problems of PLL for the study on the performance evaluation of high speed frequency hopping system design. We designed a system that practices high speed frequency hopping and interprets improvement of error-rates and evaluated its performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.206-212
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• 2008

This paper proposes the PLL(Phase-Locked Loop) algorithm by a new FFT(Fast Fourier Transform) in a grid-connected PV PCS(Photovoltaics Power Conditionning System). The grid-connected inverter that is applied in a new renewable energy field needs the grid phase information for synchronism. Unlike the PLL which is normally used by three phase D-Q conversion, the preposed PLL algorithm using FFT has non-gain tuning and the powerful noise elimination by the characteristics of FFT. Both simulation and experimental result show that proposed algorithm has the good capacity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.55-60
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• 1983

A new type of digital phase-locked loop (DPLL) that employs a multilevel quantified timing error detector (TED) is proposed and analyzed under the assumption of negligible quantizing effect and no noise. Since the timing error is quantized uniformly, the TED has a linear characteristic. From the linear characteristic of TED, a first order difference equation describing the behavior of the loop is derived. Using the system equation, the loop is analyzed mathematically for phase step and frequency step input. Desired locking condition for the loop to be locked and the lock range for the DPLL's to achieve exact locking independently of initial conditions are ob-tained. And these analyses are confirmed by timing error plane plots and computer simulation.