• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.235-240
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• 2006

Ionospheric scintillation induces a rapid change in the amplitude and phase of radio wave signals. This is due to irregularities of electron density in the F-region of the ionosphere. It reduces the accuracy of both pseudorange and carrier phase measurements in GPS/satellite based Augmentation system (SBAS) receivers, and can cause loss of lock on the satellite signal. Scintillation is not as strong at mid-latitude regions such that positioning is not affected as much. Severe effects of scintillation occur mainly in a band approximately 20 degrees on either side of the magnetic equator and sometimes in the polar and auroral regions. Most scintillation occurs for a few hours after sunset during the peak years of the solar cycle. This paper focuses on estimation of the effects of ionospheric scintillation on GPS and SBAS signals using a software receiver. Software receivers have the advantage of flexibility over conventional receivers in examining performance. PC based receivers are especially effective in studying errors such as multipath and ionospheric scintillation. This is because it is possible to analyze IF signal data stored in host PC by the various processing algorithms. A L1 C/A software GPS receiver was developed consisting of a RF front-end module and a signal processing program on the PC. The RF front-end module consists of a down converter and a general purpose device for acquiring data. The signal processing program written in MATLAB implements signal acquisition, tracking, and pseudorange measurements. The receiver achieves standalone positioning with accuracy between 5 and 10 meters in 2drms. Typical phase locked loop (PLL) designs of GPS/SBAS receivers enable them to handle moderate amounts of scintillation. So the effects of ionospheric scintillation was estimated on the performance of GPS L1 C/A and SBAS receivers in terms of degradation of PLL accuracy considering the effect of various noise sources such as thermal noise jitter, ionospheric phase jitter and dynamic stress error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of Power Electronics
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• v.18 no.1
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• pp.234-250
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• 2018

This paper presents a new load sharing control for use between paralleled three-phase inverters in an islanded microgrid based on the online line impedance estimation by the use of a Kalman filter. In this study, the mismatch of power sharing when the line impedance changes due to temperature, frequency, significant differences in line parameters and the requirements of the Plug-and-Play mode for inverters connected to a microgrid has been solved. In addition, this paper also presents a new droop control method working with the line impedance that is different from the traditional droop algorithm when the line impedance is assumed to be pure resistance or pure inductance. In this paper, the line impedance estimation for parallel inverters uses the minimum square method combined with a Kalman filter. In addition, the secondary control loops are designed to restore the voltage amplitude and frequency of a microgrid by using a combined nominal value SOGI-PLL with a generalized integral block and phase lock loop to monitor the exact voltage magnitude and frequency phase at the PCC. A control model has been simulated in Matlab/Simulink with three voltage source inverters connected in parallel for different ratios of power sharing. The simulation results demonstrate the accuracy of the proposed control method.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.673-675
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• 2004

This study proposes controller with voltage-compensated drivers for producing gray-scaled pictures on passive matrix organic light emitting diodes (PMOLEDs) panels. The controller includes voltage type drivers so the output impedance of the driver is far less than that of the current-type driver. Its low output impedance provides better electron-optical properties than those of traditional current drivers. A free running clock and a group of counters are applied to the gray-scaled function so that phase lock loop (PLL) circuit can be reduced in the controller. A pre-charge function is used to enhance performance of the luminance of an active OLED pixel. As a result, distribution of the low gray level portion is achieved linear relationship with input data. In this work, the digital part of the proposed controller is implemented using FPGA chips, and analog parts are combined with a digital-analog converter (DAC) and analog switches. A still image is displayed on a $48^{\ast}64$ PMOLEDs panel to assess the luminance performance fir the controller. Based on its cost requirement and luminance performance, the controller is qualified to join the market for driving PMOLEDs panels.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1264-1271
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• 2012

Fast tracking is important for high-speed data transmission in high-speed mobile environment such as high speed rail and vehicular. Digital retrodirective array antenna is possible to do automatically beam tracking because it can control the phase information of the output signal toward opposite direction to input signal without no a priori knowledge of the arrival direction. Also, Digital retrodirective array antennas has merit that it is easy to upgrade and modify compare with analogue retrodirective array antennas. In this paper, we analyze the BER performance of digital retrodirective array antenna under AWGN environment and multipath signal. Simulation results show correct phase estimation and conjugation of retrodirective array antenna by using phase detector block. Also, phase conjugation technique has better BER performance about 1 dB at source than that of without phase conjugation when phase lag is $15^{\circ}$ in AWGN environment. This paper also discusses effect of the presence of multipath signal. Phase and amplitude error about direction of direct signal occurs when retrodirective array system is affected by interference and multipath signal in the presence of multipath signal.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1305-1317
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• 2015

Distributed generation systems (DGSs) have been getting more and more attention in terms of renewable energy use and new generation technologies in the past decades. The self-excited induction generator (SEIG) occupies an important role in the area of energy conversion due to its low cost, robustness and simple control. Unlike synchronous generators, the SEIG has to absorb capacitive reactive power from the outer device aiming to stabilize the terminal voltage at load changes. This paper presents a novel static VAR compensator (SVC) called a magnetic energy recovery switch (MERS) to serve as a voltage controller in SEIG powered DGSs. In addition, many small scale SEIGs, instead of a single large one, are applied and devoted to promote the generation efficiency. To begin with, an expandable mathematic model based on a d-q equivalent circuit is created for parallel SEIGs. The control method of the MERS is further improved with the objective of broadening its operating range and restraining current harmonics by parameter optimization. A hybrid control strategy is developed by taking both of the stand-alone and grid-connected modes into consideration. Then simulation and experiments are carried out in the case of single and double SEIG(s) generation. Finally, the measurement results verify that the proposed DGS with SVC-MERS achieves a better stability and higher feasibility. The major advantages of the mentioned variable reactive power supplier, when compared to the STATCOM, include the adoption of a small DC capacitor, line frequency switching, simple control and less loss.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.717-724
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• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.