• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• 한국산학기술학회논문지
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• 제19권1호
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• pp.105-112
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• 2018

본 논문은 로이유리(Low emissivity glass) 표면에 증착되어 있는 금속박막의 전도 특성을 이용하여 발열유리(Heatable glass)를 제작하는 방법에 대해 제안한다. 로이유리의 발열량은 로이유리 표면저항에 의한 주울(Joule) 열에 의존하므로 소재의 표면저항을 측정함으로써 예측 및 설계가 가능하다. 본 연구에서는 저방사층이 11nm인 소프트로이유리 시료에 각 50mm 간격으로 은(Ag) 전극을 형성시키고, 4단자법으로 면저항을 측정하여 로이유리의 소비전력과 발열량을 예측한 후에, 제작 및 실험을 통해 발열성능을 확인하였다. 기존의 발열유리 제작방법은 크게 두 가지로 일반유리(Normal glass)에 니크롬(Nichrome) 열선을 삽입하는 방법과, 일반유리에 전도성 투명박막을 증착하는 방법이 있다. 니크롬 열선 삽입 방식은 발열성능은 우수하나 유리 고유의 투명성을 저해하고, 전도성 투명박막을 증착하는 방법은 투명성은 양호하나 공정이 복잡하여 실용성이 저하된다. 본 논문에서는 주로 건축물의 단열효과 향상을 위해 사용되는 로이유리를 이용하여 로이유리 전면에 코팅되어 있는 전도성 금속박막에 레이저 빔을 조사하여 원하는 발열성능을 가지는 발열유리를 제작하는 방법을 제안한다. 제안된 방법은 기존의 니크롬 열선을 삽입하는 방법에 비해 투명성이 양호하고, 전도성 투명박막을 증착하는 방법에 비해 제작과정이 보다 수월함을 확인하였다. 아울러, 레이저를 조사하여 로이유리의 표면 박막을 패터닝(Patterning) 하는 형태에 따른 발열특성의 비교와 로이유리에 적합한 레이저 출력조건을 제시하고자 한다.

• 마이크로전자및패키징학회지
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• 제28권1호
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• pp.47-54
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• 2021

미세화 되고 있는 PCB 솔더 범프 접합을 위해 종래 마이크로 볼에 의한 PCB 솔더 범프의 제조를 대신하여 주석 전기도금을 통한 패턴을 제작하기 위한 도금액을 제작하고 도금공정 조건을 찾는 실험을 진행하였다. SR 패터닝 후에 Cu 씨드층을 형성하고, 다시 DFR 패터닝을 통해 PCB 기판상에 선택성장이 가능한 패턴을 제작하였다. 도금액은 메탄술폰산을 기본액으로 하는 주석도금액을 사용하였으며, 2가의 주석이온의 산화를 방지하기 위해 hydroquinone을 첨가하였다. 표면활성제로는 Triton X-100를 사용하고, 결정립 미세화를 위해 gelatin을 첨가하여 시료를 제작하였다. 전기화학적 분극곡선을 측정함으로써, Triton X-100 및 gelatin 첨가제의 작용 특성을 비교하였으며, gelatin이 -0.7 V vs. NHE까지 수소발생을 억제하는 것에 비해 Triton X-100을 첨가하게 되면 -1 V vs. NHE까지 수소발생이 억제되는 것을 확인할 수 있었다. 결정립의 크기는 전류밀도가 증가하면서 미세화되는 일반적 경향을 나타내었으며, gelatin을 첨가하는 경우에 보다 더 미세해지는 것이 관찰되었다.

• 한국재료학회지
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• 제15권10호
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• pp.626-631
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• 2005

GaN-related compound semiconductors were grown on the corrugated interface substrate using a metalorganic chemical vapor deposition system to increase the optical power of white LEDs. The patterning of substrate for enhancing the extraction efficiency was processed using an inductively coupled plasma reactive ion etching system and the surface morphology of the etched sapphire wafer and that of the non-etched surface were investigated using an atomic force microscope. The structural and optical properties of GaN grown on the corrugated interface substrate were characterized by a high-resolution x-ray diffraction, transmission electron microscopy, atomic force microscope and photoluminescence. The roughness of the etched sapphire wafer was higher than that of the non-etched one. The surface of III-nitride films grown on the hemispherically patterned wafer showed the nano-sized pin-holes that were not grown partially. In this case, the leakage current of the LED chip at the reverse bias was abruptly increased. The reason is that the hemispherically patterned region doesn't have (0001) plane that is favor for GaN growth. The lateral growth of the GaN layer grown on (0001) plane located in between the patterns was enhanced by raising the growth temperature ana lowering the reactor pressure resulting in the smooth surface over the patterned region. The crystal quality of GaN on the patterned substrate was also similar with that of GaN on the conventional substrate and no defect was detected in the interface. The optical power of the LED on the patterned substrate was $14\%$ higher than that on the conventional substrate due to the increased extraction efficiency.

• 한국정밀공학회지
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• 제30권6호
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• pp.589-595
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• 2013

Solution processed conjugated molecules enable to manufacture various electronic devices by unconventional and cost effective patterning methods as screen or gravure printing. Spin-coating is the most popularly used method to form conjugated polymeric film for various electronic devices. The coating method has certain disadvantages such as a large amount of unwanted wastes, difficulty forming a film with a large area, and impossible to apply roll-to-roll manufacturing. We present here a promising alternative coating method, bar-coating for conjugated polymer film and OLED with the bar coated light emitting layer. In this papers, we show atomic force microscope images of spin- and bar-coated Poly[(9,9-di-n-octylfluorenyl-2,7-diyl)-alt-(benzo[2,1,3]thiadiazol-4,8-diyl)] (F8BT) films on substrate. The bar-coated film showed a slight lower RMS roughness (1.058 [nm]) than spin-coated film (1.767 [nm]). It means the bar-coating is suitable method to form light emitting layers in OLEDs. By using bar-coating process, an OLED obtained with 4.7 [cd/A] in maximum current efficiency.

• 한국광학회:학술대회논문집
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• 한국광학회 2009년도 동계학술발표회 논문집
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• pp.133-134
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• 2009

Cold temperature development (CTD) of electron beam (EB) patterned resists and subsequent dry etching were investigated for fabrication of nano-patterned Niobium (Nb). Bulky Nb fims on GaAs substrates were deposited with EB evaporation. Line patterns on Nb cathode were fabricated by EB patterning and reactive ion etching (RIE). Size deviations of nano-sized line patterns from CAD designed patterns are dependent on the EB total exposure, but it can be improved by CTD of EB-exposed resist. Line patterns of 10 to 300 nm widths of EB-exposed resist patterns were drawn under various exposure conditions of $0.2{\mu}s$/dot (total 240,000 dot) with a constant current (50 pA). Compared with room temperature development (RTD), the CTD improves pattern resolution due to the suppression of backscattering effect. RIE with $CF_4$ was performed for formation of several nano-sized line patterns on Nb. Each EB-resist patterned samples with RTDs and CTDs were etched with two different $CF_4$ gas pressures of 5 Pa. Nb etching rate increases while GaAs (or ZEP) etching rate decreases as the chamber pressure increases. This different dependent of the etching rate on the $CF_4$ pressure between Nb and GaAs (or ZEP) has a significant meaning because selective etching of nano-sized Nb line patterns is possible without etching of the underlying active layer.

• 한국전기전자재료학회논문지
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• 제31권3호
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• pp.129-134
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• 2018

Herein, we report the manufacture of high-performance, ambipolar organic field-effect transistors (OFETs) and complementary-like electronic circuitry based on a blended, polymeric, semiconducting film. Relatively high and well-balanced electron and hole mobilities were achieved by incorporating a small amount of ionic additives. The equivalent P-channel and N-channel properties of the ambipolar OFETs enabled the manufacture of complementary-like inverter circuits with a near-ideal switching point, high gain, and good noise margins, via a simple blanket spin-coating process with no additional patterning of each active P-type and N-type semiconductor layer.

• 한국광학회지
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• 제15권1호
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• pp.79-85
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• 2004

후면의 석영면에 위상 패턴을 형성하여 투과율 조절을 구현한 포토마스크에 대해 보고한다. 위상 패턴의 크기와 패턴 조밀도에 따른 조명 동공의 형태 변화에 관한 이론적 결과와 투과율 조절 포토마스크를 사용한 웨이퍼 상 CD(critical dimension) 균일도 개선에 관한 실험적 결과에 대해 기술한다. 투과율 조절을 위한 위상 패턴은 패턴이 형성되지 않은 영역에 대해 180$^{\circ}$의 상대적 위상을 갖도록 석영면을 식각한 콘택홀 형태의 패턴을 사용하였다. 콘택홀 패턴의 크기가 작을수록 본래의 조명동공 형태를 유지하게 되며, 동일한 패턴 조밀도에서 더욱 큰 노광 광세기 저하가 일어남을 알 수 있었다. 패턴 조밀도를 위치별로 변화시켜 CD균일도 개선에 적합한 투과율 분포를 포토마스크 후면에 형성하였다. 투과율 조절 포토마스크를 140nm 디자인 롤을 갖고 있는 DRAM(Dynamic Random Access Memory)의 한 주요 레이어에 적용하여 CD 균일도를 3$\sigma$값으로 24.0nm에서 10.7nm 로 개선할 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 디스플레이 광소자분야
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• pp.86-89
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• 2004

Organic thin film transistors (OTFTs) are fabricated on the plastic substrate through 4-level mask process without photolithographic patterning to yield the simple fabrication process. And we herewith report for the effect of dielectric surface modification on the electrical characteristics of OTFTs. The KIST-JM-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide $(ZrO_2)$ gate dielectric layer. In this work, we have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.259-259
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• 2010

Periodically polarity inverted (PPI) ZnO structures on (0001) Al2O3 substrates are demonstrated by plasmas assisted molecular beam epitaxy. The patterning and re-growth methods are used to realize the PPI ZnO by employing the polarity controlling method. For the in-situ polarity controlling of ZnO films, Cr-compound buffer layers are used.[1, 2] The region with the CrN intermediate layer and the region with the Cr2O3 and Al2O3 substrate were used to grow the Zn- and O-polar ZnO films, respectively. The growth behaviors with anisotropic properties of PPI ZnO heterostructures are investigated. The periodical polarity inversion is evaluated by contrast images of piezo-response microscopy. Structural and optical interface properties of PPI ZnO are investigated by the transmission electron microcopy (TEM) and micro photoluminescence ($\mu$-PL). The inversion domain boundaries (IDBs) between the Zn and the O-polar ZnO regions were clearly observed by TEM. Moreover, the investigation of spatially resolved local photoluminescence characteristics of PPI ZnO revealed stronger excitonic emission at the interfacial region with the IDBs compared to the Zn-polar or the O-polar ZnO region. The possible mechanisms will be discussed with the consideration of the atomic configuration, carrier life time, and geometrical effects. The successful realization of PPI structures with nanometer scale period indicates the possibility for the application to the photonic band-gap structures or waveguide fabrication. The details of application and results will be discussed.