• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.2
• /
• pp.94-102
• /
• 2020

Considering that the output voltage and current of a single PV panel are limited in PV power generation, a PV array should be constructed by connecting several PV panels in series and parallel to meet the required voltage/power levels for power generation capacity. When a PV array is partially shaded, the maximum power generation depends on the configuration of a PV array and the presence or absence of blocking diodes. This study considers six PV array configurations and the presence or absence of blocking diodes. An optimum connection structure was proposed to maximize power generation in a partial shadow condition. Results were verified through simulation and an experiment.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.6 no.12
• /
• pp.3296-3314
• /
• 2012

We present a novel approach for the simulation of color pencil effects using line integral convolution (LIC) to produce pencil drawings from images. Our key idea is to use a bilateral convolution filter to simulate the various effects of pencil strokes. Our filter resolves the drawbacks of the existing convolution-based schemes, and presents an intuitive control to mimic the properties of pencil strokes. We also present a scheme that determines stroke directions from the shapes to be drawn. Smooth tangent flows are used for the pixels close to feature lines, and partially parallel flows inside regions. The background is rendered using a flow of fixed direction. Using different styles of stroke directions increases the realism of the resulting images. This approach produces convincing pencil drawing effects from photographs.

• Proceedings of the Polymer Society of Korea Conference
• /
• 2006.10a
• /
• pp.99-100
• /
• 2006

Orthogonally protected block copolymers of based on p-hydroxystyrene were prepared with high control via nitroxy mediated radical polymerization using an alkoxyamine as an unimolecular initiator. Thin films of partially protected block copolymer were prepared by spin or dip coating. A well defined nanostructure could be observed as a result of phase separation e.g. cylinders in a matrix oriented perpendicular or parallel to the substrate. The nanostructure of the polymeric films can be defined by the block copolymer composition and it determines surface properties and allows further, selective functionalization, e.g. via click chemistry. The thin films can be designed in a way to allow a patterning based on a thermal or photochemical stimulus.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.118-124
• /
• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• KIPS Transactions on Computer and Communication Systems
• /
• v.2 no.10
• /
• pp.413-420
• /
• 2013

Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

• Journal of The Korean Association of Information Education
• /
• v.18 no.3
• /
• pp.371-380
• /
• 2014

There is a little curriculum for gifted and talented elementary information. Generally parallel curriculum model(PCM) for gifted children is being applied to many subjects. It is necessary to apply the PCM for gifted elementary children of information science. This model is a prime example of a training program was applied to the encryption. There are four parallel curriculum model. The four curriculum model can be used individually or combined, may be used only partially. In this study, the benefits of parallel curriculum model in order to reflect as much as possible in order all four courses were used. This program for 19 students in the gifted children for information science class were applied to four periods. Observe and record the activities of students in class, the survey targeted learners, assignments, methods of analysis were used. We found that the level of the program was suitable and the aspects of giftedness such as an ability to focus on the task and an ability to solve the problem were enhanced. Moreover, participants became more interested in the topic of encryption following the program.

• Korean Journal of Fisheries and Aquatic Sciences
• /
• v.42 no.6
• /
• pp.683-694
• /
• 2009

High-resolution (Chirp and Sparker system) seismic profiles were analyzed to investigate the sedimentary sequence and distribution pattern of the late Holocene deposits in Gyunggi Bay, the Yellow Sea. The bay is located in the western part of Korea, east of the Yellow Sea. The sedimentary sequence divided into three units bounded by erosional bounding surface: (1) acoustically parallel to subparallel reflectors with cross bedding structures (Unit 1); (2) confused inner reflectors and top of unit exposed partially at the seafloor (Unit 2); and (3) approximately parallel reflections and regressive to transgressive incision-fills (Unit 3). On the basis of seafloor morphology, surface bedforms, and subbotom acoustic characters, echo types in the study area were identified following the schemes of Chough et al. (2002); (1) flat seafloor with sharp bottom echoes (echo types 1-1, 1-2 and 1-3; transgressive sediment sheets or relict sands), (2) mounded seafloor with either smooth surface or superposed bedforms (echo types 2-1 and 2-2; tidal ridges), and (3) various-scale eroded seafloor (echo types 3-1 and 3-2; channels). Suspect features of acoustic turbid zones which is related to gas charged sediment are reported.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.4A
• /
• pp.414-422
• /
• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.11
• /
• pp.1248-1255
• /
• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.7 no.10
• /
• pp.2479-2496
• /
• 2013

Increasing demand for Full High-Definition (FHD) video and Ultra High-Definition (UHD) video services has led to active research on high speed video processing. Widespread deployment of multi-core systems has accelerated studies on high resolution video processing based on parallelization of multimedia software. Even if parallelization of a specific decoding step may improve decoding performance partially, such partial parallelization may not result in sufficient performance improvement. Particularly, entropy decoding has often been considered separately from other decoding steps since the entropy decoding step could not be parallelized easily. In this paper, we propose a parallelization technique called Integrated Multi-Threaded Parallelization (IMTP) which takes parallelization of the entropy decoding step, with other decoding steps, into consideration in an integrated fashion. We used the Simultaneous Multi-Threading (SMT) technique with appropriate thread scheduling techniques to achieve the best performance for the entire decoding step. The speedup of the proposed IMTP method is up to 3.35 times faster with respect to the entire decoding time over a conventional decoding technique for H.264/AVC videos.