• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.607-610
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• 2003

The characteristic prediction and analysis of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. The four different structures of 3-D inductor are fabricated by using low-temperature cofired ceramic (LTCC) process. The circuit model parameters of the each building block are optimized and extracted using the partial element equivalent circuit method and HSPICE circuit simulator. Based on the model parameters, predictive modeling is applied for the structures composed of the combination of the modeled building blocks. And the characteristics of test structures, such as self-resonant frequency, inductance and Q-factor, are analyzed. This approach can provide the characteristic conception of 3-D solenoid embedded inductors for structural variations.

• Journal of Power Electronics
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• v.9 no.2
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• pp.308-319
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• 2009

An increasing number of power electronic applications require high power density. Therefore, the switching frequency and switching speed have to be raised considerably. However, the very fast switching transients induce a strong voltage and current ringing. In this work, a novel damping concept is introduced where the parasitic wiring inductances are advantageously magnetically coupled with a damping layer for attenuating these unwanted oscillations. The proposed damping layer can be implemented using standard materials and printed circuit board manufacturing processes. The system behavior is analyzed in detail and design guidelines for a damping layer with optimized RC termination network are given. The effectiveness of the introduced layer is determined by layout parasitics which are calculated by application of the Partial Element Equivalent Circuit (PEEC) simulation method. Finally, simulations and measurements on a laboratory prototype demonstrate the good performance of the proposed damping approach.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.3
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• pp.122-129
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• 2001

Exact simulation of conducted EMI in switched mode power supplies is proposed. In order to achieve exact simulation, PSPICE active component ABM model and modified transformer model are proposed. Each model parameter is extracted from measurements and data-books. PSPICE simulation results with high frequency PCB pattern model are accordant with EMI measurements for a 50[W] isolated flyback converter. EMI relations of each component and EMI patterns are analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.49-60
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• 2002

A systematic design approach for Power distribution network (PDN) is presented aiming at applications to DRAM module designs. Three main stages are comprised in this design approach: modeling and simulation of a PDN based on a two-dimensional transmission line structure employing a partial element equivalent circuit (PEEC); verification of the simulation results through comparison to measured values; and design space scanning with PDN parameters. Impedance characteristics for do-coupling capacitors are analyzed to devise an effective way to stabilize power and ground plane Performance within a target level of disturbances. Self-impedance and transfer-impedance are studied in terms of distance between circuit features and the size of do-coupling capacitors. A simple equation has been derived to find the do-coupling capacitance values yielding impedance lower than design target, and thereby reducing the overall computation time. The effectiveness of the design methodology has been demonstrated using a DRAM module with discrete do-coupling capacitors and a strip structure.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.