• Current Optics and Photonics
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• v.2 no.5
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• pp.400-406
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• 2018

The Semiconductor Optical Amplifier (SOA)-based Mach-Zehnder interferometer is a major contributor in all-optical digital processing and optical computation. Optical tree architecture provides one of the new, alternative schemes for integrated all-optical arithmetic and logical operations. In this paper, we propose an all-optical 3-bit integrated parity generator and checker using SOA-MZI-based optical tree architecture. The proposed scheme, able to process input signals at a desired operating wavelength, has been characterized using RZ-modulated signals at 10 Gbps. The maximum extinction ratios achieved at the output of the parity generator and checker are 10 dB and 8 dB respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.619-625
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• 2009

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.1
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• pp.52-60
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• 1999

This paper deals with a fault detection and isolation scheme for a DC motor driven centrifugal pump system. The emphasis is placed on the design and implementation of the residual generatorm, based on parity relation, that provides decision logic unit with residuals that will be further processed to detect and isolate three important faults in the system;brush fault, impeller fault, and the speed sensor fault. Two process faults are modelled as multiplicative type faults, while the sensor fault as an additive one. With multiplicative fault, the implementation of the residual generator needs the time varying transformation matrix that must be computed on-line. Typical implementation methods lack in generality because only a numerical approximation around the assumed fault levels is employed. In this paper, a new implementation method using well tranined neural network is proposed to improve the generality of the residual generator. Application results show that the fault detection and isolation scheme with the proposed residual generator effectively isolates three major faults in the centrifugal pump system even with a wide range of fault magnitude.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1440-1443
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• 1997

The optimal residual generator based on parity relation approach for the fault detection and isolation of a arge diesel engine actuator position servo system is presented. The closed-loop residual generator is designed to have robustness against modeling errors and noise. Main purpose of the fault detection and isolation system in the process is to detect and isolate two important faults, i.e., actuatro fault and fault of speed sensor, that, if not detected and compensated, degrade the overall control system performance. Simulation results are give to show the practical applicability of the fault detecrtion and isloation scherme.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1991.11a
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• pp.40-48
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• 1991

McEliece 공개키 암호체계에 대한 새로운 암호해독적 공격이 제시되어진다. 기존의 암호해독 algorithm이 exponential-time의 complexity를 가지는 반면, 본고에서 제시되어지는 algorithm은 polynomial-time의 complexity를 가진다. 모든 linear codes에는 systematic generator matrix가 존재한다는 사실이 본 연구의 동기가 된다. Public generator matrix로부터, 암호해독에 사용되어질 수 있는 새로운 trapdoor generator matrix가 Gauss-Jordan Elimination의 역할을 하는 일련의 transformation matrix multiplication을 통해 도출되어진다. 제시되어지는 algorithm의 계산상의 complexity는 주로 systematic trapdoor generator matrix를 도출하기 위해 사용되는 binary matrix multiplication에 기인한다. Systematic generator matrix로부터 쉽게 도출되어지는 parity-check matrix를 통해서 인위적 오류의 수정을 위한 Decoding이 이루어진다.

• Bulletin of the Korean Mathematical Society
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• v.57 no.2
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• pp.459-479
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• 2020

In the last two decades, codes over noncommutative rings have been one of the main trends in coding theory. Due to the fact that noncommutativity brings many challenging problems in its nature, still there are many open problems to be addressed. In 2015, generator polynomial matrices and parity-check polynomial matrices of generalized quasi-cyclic (GQC) codes were investigated by Matsui. We extended these results to the noncommutative case. Exploring the dual structures of skew constacyclic codes, we present a direct way of obtaining parity-check polynomials of skew multi-twisted codes in terms of their generators. Further, we lay out the algebraic structures of skew multipolycyclic codes and their duals and we give some examples to illustrate the theorems.

• Proceedings of the KIEE Conference
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• 1998.07b
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• pp.819-821
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• 1998

This paper deals with a method or a residual generation for fault isolation in a centrifugal pump with a water circulation system, driven by a speed controlled dc motor. It is based on parity relations derived from the moving-average model of the system and is used to identify sensor faults and two possible brush and impeller faults, where the former is dealt with additive faults, while the latter characterized as discrepancies between the nominal and actual plant parameters of the system is modelled by multiplicative faults. We will represent the propagation of this uncertainty to the model matrices by the approximate handling of partial derivatives of polynomials. With multiplicative faults, the transformation matrix implemented in the residual generator are calculated on-line. The simulation studies demonstrate that small changes of the system can be detected and diagnosed by using the method.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1033-1036
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• 1999

This paper proposes an efficient fault diagnosis for digital circuits using multilayer neural networks. The efficient learning algorithm is also proposed for the multilayer neural network, which is combined the steepest descent for high-speed optimization and the dynamic tunneling for global optimization. The fault-diagnosis system using the multilayer neural network of the proposed algorithm has been applied to the parity generator circuit. The simulation results shows that the proposed system is higher convergence speed and rate, in comparision with system using the backpropagation algorithm based on the gradient descent.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.42-49
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• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.