• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.28-38
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• 2013

In this paper, we propose a improved turbo equalizer which generates a feedback signal through a simple calculation to improve performance in single carrier system with the LMS(least mean square) algorithm based equalizer and LDPC(low density parity check) codes. LDPC codes can approach the Shannon limit performance closely. However, computational complexity of LDPC codes is greatly increased by increasing the repetition of the LDPC codes and using a long parity check matrix in harsh environments. Turbo equalization based on LDPC code is used for improvement of system performance. In this system, there is a disadvantage of very large amount of computation due to the increase of the repetition number. To less down the amount of this complicated calculation, The proposed improved turbo equalizer adjusts the adoptive equalizer after the soft decision and the LDPC code. Through the simulation results, it's confirmed that performance of improved turbo equalizer is close to the SISO-MMSE(soft input soft output minimum mean square error) turbo equalizer based on LDPC code with the smaller amount of calculation.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.665-671
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• 2010

In this paper, a turbo equalizer is proposed for the digital video broadcasting for terrestrial - 2nd generation (DVB-T2) system. The proposed turbo equalizer is consisted with the maximum a posteriori (MAP) and low density parity check (LDPC) decoder. The channel information for the soft-input-soft-output (SISO) MAP equalizer is based on the least square (LS) channel estimator. The performance is analyzed through computer simulations in terms of the iteration number.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.758-763
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• 2008

We introduce a noise-predictive turbo equalization using noise filter in perpendicular magnetic recording(PMR) channel. The noise filter mitigates the colored noise in high-density PMR channel. In this paper, the channel detectors used are SOVA (Soft Output Viterbi Algorithm) and BCJR algorithm which proposed by Bahl et al., and the outer decoder used is LDPC (Low Density Parity Check) code that is implemented by sum-product algorithm. Two kinds of LDPC codes are experimented. One is the 0.5Kbyte (4336,4096) LDPC code with the code rate of 0.94, and the other is 1Kbyte (8432,8192) LDPC code with the code rate of 0.97.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.317-319
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• 1993

The function estimation characteristics of neural networks can be used for sensor signal validation of a system. In case of applying the neural networks to signal validation, it is a important problem that the redundant sensor signals used as a input signal of neural networks should be validated. In this paper, we simplify the conventional parity space method in order to input the validated signal to the neural networks and also propose the sensor signal validation method, which estimates the reliable sensor output combining neural networks with the simplified parity space method. The acceptability of the proposed signal validation method is demonstrated by using the simulation data in safety injection accident of nuclear power plants.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.8
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• pp.1-11
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• 2012

The multi-code spread spectrum communication system, which spreads data bit stream by multiplexing orthogonal codes, can transmit data in high rate. However it needs the high-cost good linear amplifier because of the multi-level output signal. In order to overcome this drawback several systems making the amplitude of output signal constant with Walsh codes have been proposed. Recently constant amplitude pre-coded multi-code spread spectrum systems using extended m-sequence have been proposed. In this paper we consider an extended m-sequence based constant amplitude multi-code spread spectrum system with code set partitioning. By grouping the orthogonal codes into 4 subsets, not only is the computational complexity of the transceiver reduced but BER performance also improves. It has been shown that parity checking on four detected codes at the receiver can correct code detection error and result in BER performance enhancement. In this paper we propose a improved parity check receiver. We carried out computer simulation to verify feasibility of the proposed algorithm.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.891-892
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• 2008

본 논문에서는 최근 주목받고 있는 에러 정정 기법 중 하나인 LDPC(Low Density Parity Check) 부호를 광 기록 채널(Optical Recording Channel)에 적용해 보았고 이때 사용되는 연판정 출력 알고리즘으로 MAP과 SOVA를 이용하여 성능을 비교하였다.