• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.952-960
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• 2012

In the distributed video coding (DVC) system, the difference between the side information and the original Wyner-Ziv frame is corrected using channel codes and the additional parity bits are requested through feedback channel if the error is not corrected. The efficient bit rate control is important to use the DVC system in the band-limited channel, such as mobile communication environments. In this paper, the constant bit rate control method in the encoder of the DVC system is proposed. The coding performance as well as the bit rate is efficiently controlled by the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3A
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• pp.151-156
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• 2012

In this paper, design of quasi-cyclic(QC) low-density parity-check codes is proposed to have full diversity for space-time bit-interleaved coded modulation(ST-BICM) systems. Necessary and sufficient conditions that the proposed scheme has full diversity are proved as the condition that submatrices corresponding to the system part of codewords are invertible. And new construction method of binary invertible matrices for QC LDPC codes in ST-BICM systems are also proposed and modification for parity-check matrices are also explained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.331-340
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• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.490-495
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• 1999

In this paper, a method of improving the learning time and convergence rate is proposed to exploit the advantages of artificial neural networks and fuzzy theory to neuron structure. This method is applied to the XOR Problem, n bit parity problem which is used as the benchmark in neural network structure, and recognition of digit image in the vehicle plate image for practical image application. As a result of the experiments, it does not always guarantee the convergence. However, the network showed improved the teaming time and has the high convergence rate. The proposed network can be extended to an arbitrary layer Though a single layer structure Is considered, the proposed method has a capability of high speed 3earning even on large images.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.891-898
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• 2014

The DVC (Distributed Video Coding) provides a theoretical basis for the implementation of light video encoder. Conventionally, lots of studies have been focused on the codec scheme of Stanford University that has a feedback channel to control the bit rate finely. However, the codec scheme can not evaluate the qualities of the frames reconstructed by the received parity bits at the decoder side. This paper presents an efficient method of estimating distortion by correcting the virtual channel noises in side information and then facilitating the measurements of the visual qualities. Through several simulations, it is shown that the proposed method is very efficient in estimating the visual qualities of the reconstructed WZ frames.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.515-520
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• 2014

In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

• Journal of Communications and Networks
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• v.12 no.4
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• pp.366-374
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• 2010

Coded cooperation is a promising user cooperation scheme. In this paper, we first propose a novel network-coding-based coded cooperation scheme. When a user decodes its partner's information correctly in the first frame, it transmits the combination of the partner's parity bits and its own parity bits through network coding in the second frame. This is distinct from the classical scheme, where the user only transmits the partner's parity bits during cooperation. We analyze the outage probability of the proposed scheme, and show that it achieves a full diversity order. Numerical evaluations reveal that the proposed scheme outperforms the classical scheme when the inter-user channel is poor, yet is worse when the inter-user channel is strong. Also, the results show that the proposed scheme always outperforms that of no cooperation in various channel conditions while the performance of classical scheme is worse than that of no cooperation with the poor inter-user channels. This means that the performance of the proposed scheme is more stable than the classical scheme and the proposed scheme is more tolerant to the poor inter-user channels. To combine the advantages of the proposed scheme and the classical scheme under different inter-user channel conditions, we propose an adaptive solution. This adaptive scheme enhances the system performance considerably in all channel conditions in spite of the inter-user channel quality, at the expense of only one acknowledgement or non-acknowledgement bit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.