• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.432-438
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• 2010

In this paper we study the effect of bit-to-symbol mappings on the convergence behavior of turbo equalizers employing low-density parity-check (LDPC) codes over high order modulations. We analyze the effective SNR of the outputs from linear minimum mean-squared error (MMSE) equalizers and the convergence property of LDPC decoding for different symbol mappings. Numerical results show that the bit-reliability (BR) mapping provides better performance than random mapping in LDPC-coded turbo equalizers over high order modulations. We also verify the effect of symbol mappings through the noise threshold and error performance.

• ETRI Journal
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• v.45 no.3
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• pp.404-417
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• 2023

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10^-10 at 3.5 dB E_b/N₀ than conventional LDPC codes, which showed a BER of 10^-7 at 3 dB E_b/N₀. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10^-6 at 4.2 dB E_b/N₀ was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

• ETRI Journal
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• v.29 no.3
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• pp.381-389
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• 2007

In this paper we propose a graph-theoretic method based on linear congruence for constructing low-density parity check (LDPC) codes. In this method, we design a connection graph with three kinds of special paths to ensure that the Tanner graph of the parity check matrix mapped from the connection graph is without short cycles. The new construction method results in a class of (3, ${\rho}$)-regular quasi-cyclic LDPC codes with a girth of 12. Based on the structure of the parity check matrix, the lower bound on the minimum distance of the codes is found. The simulation studies of several proposed LDPC codes demonstrate powerful bit-error-rate performance with iterative decoding in additive white Gaussian noise channels.

• Journal of Communications and Networks
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• v.13 no.3
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• pp.205-210
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• 2011

This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.2 s.314
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• pp.11-18
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• 2007

Back propagation algorithm based on a gradient-decent method has been widely used to the training of a neural network. However, this algorithm have some problems such as dropping the minimum value in a local area according to an initial value and setting the number of units in a hidden layer when training the neural network. Accordingly, to solve the above-mentioned problems, this paper proposes a genetic algorithm using the training method of the neural network. Thus, the improved genetic algorithm using a new crossover and mutation method is proposed to discriminate 3 bit parity. Experiments confirm that the proposed system is effective for training speed after demonstrating for generation gap, the number of units in the hidden layer, and the number of individuals.

• ETRI Journal
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• v.31 no.5
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• pp.619-621
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• 2009

In this letter, we study the influence of receiver imperfections on bit error rate (BER) degradations in detecting low-density parity-check coded multilevel phase-shift keying signals transmitted over a Rician fading channel. Based on the analytical system model which we previously developed using Monte Carlo simulations, we determine the BER degradations caused by the simultaneous influences of stochastic phase error, quadrature error, in-phase-quadrature mismatch, and the fading severity.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

• ETRI Journal
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• v.32 no.4
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• pp.603-606
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• 2010

In this letter, we propose a channel estimation algorithm based on incremental pilots. These are pilots additionally inserted after puncturing the modulated orthogonal frequency division multiplexing (OFDM) symbols to enhance channel estimation performance without lowering bandwidth efficiency. A low-density parity-check code puncturing scheme is also proposed to prevent the performance degradation due to the codeword bit loss caused by punctured OFDM symbols.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.149-152
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• 2009

본 논문에서는 오차역전파 알고리즘을 사용한 3층 구조의 퍼셉트론형 신경회로망으로 네트워크의 학습을 실시하여, N비트의 패리티판별에 필요한 최소의 중간유닛수의 해석에 관한 연구이다. 따라서 본 논문은 제안한 퍼셉트론형 신경회로망의 중간 유닛의 수를 변화시켜 N 비트의 패리티 판별 실험을 실시하였다. 본 시스템은 패리티 판별의 실험을 통하여 N 비트 패리티 판별이 가능하다는 것을 실험으로 확인한다.