• Title/Summary/Keyword: Parity Bit

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A Study about Performance of Sum-Product Decoder Considering Adaptive Bit-Loading in LDPC Coded OFDM Systems (LDPC Coded OFDM 시스템에서 적응형 비트 로딩을 고려한 Sum-Product 복호기 성능에 관한 연구)

  • Oh, Hui-Myoung;Kim, Young-Sun;Lee, Jae-Jo
    • Proceedings of the KIEE Conference
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    • 2006.07d
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    • pp.2027-2028
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    • 2006
  • 추정된 채널 정보를 바탕으로 적용하는 적응형 비트 로딩 방식은, 전력선 통신 시스템의 고속화 및 대용량 데이터 전송을 위해 최근 대두되고 있는 LDPC(Low Density Parity Check) coded OFDM 시스템에 대해, 한정된 주파수 대역과 신호 전력의 효율적 사용을 제공한다. 그러나 적응형 비트로딩 방식은 한정된 수의 일정 SNR(신호대 잡음 전력비) 구간에 대한 mapping 방식으로 적용되기 때문에 송수신 과정에서 추정된 채널 정보를 이용하는 sum-product 복호기가 채널 변화에 민감하게 반응하지 못하는 상황이 발생하며, 결국 송신단에서 채널 추정 결과를 바탕으로 선택된 SNR 범위에 대해서는 실제 수신되는 신호에 대한 SNR과의 차이가 존재하고 시스템의 성능은 그 만큼의 성능 열하로 나타나게 된다. 본 논문에서는 이러한 성능 열하 정도를 시뮬레이션을 통해 확인하였다.

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A Low-Complexity CLSIC-LMMSE-Based Multi-User Detection Algorithm for Coded MIMO Systems with High Order Modulation

  • Xu, Jin;Zhang, Kai
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.4
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    • pp.1954-1971
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    • 2017
  • In this work, first, a multiuser detection (MUD) algorithm based on component-level soft interference cancellation and linear minimum mean square error (CLSIC-LMMSE) is proposed, which can enhance the bit error ratio (BER) performance of the traditional SIC-LMMSE-based MUD by mitigating error propagation. Second, for non-binary low density parity check (NB-LDPC) coded high-order modulation systems, when the proposed algorithm is integrated with partial mapping, the receiver with iterative detection and decoding (IDD) achieves not only better BER performance but also significantly computational complexity reduction over the traditional SIC-LMMSE-based IDD scheme. Extrinsic information transfer chart (EXIT) analysis and numerical simulations are both used to support the conclusions.

Implementation of Hybrid Neural Network for Improving Learning ability and Its Application to Visual Tracking Control (학습 성능의 개선을 위한 복합형 신경회로망의 구현과 이의 시각 추적 제어에의 적용)

  • 김경민;박중조;박귀태
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.12
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    • pp.1652-1662
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    • 1995
  • In this paper, a hybrid neural network is proposed to improve the learning ability of a neural network. The union of the characteristics of a Self-Organizing Neural Network model and of multi-layer perceptron model using the backpropagation learning method gives us the advantage of reduction of the learning error and the learning time. In learning process, the proposed hybrid neural network reduces the number of nodes in hidden layers to reduce the calculation time. And this proposed neural network uses the fuzzy feedback values, when it updates the responding region of each node in the hidden layer. To show the effectiveness of this proposed hybrid neural network, the boolean function(XOR, 3Bit Parity) and the solution of inverse kinematics are used. Finally, this proposed hybrid neural network is applied to the visual tracking control of a PUMA560 robot, and the result data is presented.

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Error Detection using Advanced Parity Bit (패리티 비트를 확장한 오류 검사에 관한 연구)

  • Kim, In-Soo;Min, Hyoung-Bok;Kim, Yong-Hyun;Kim, Shin-Taek
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1965-1966
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    • 2008
  • The manipulation of Boolean functions is a fundamental part of computer science, and many problems in the design and testing of digital systems can be expressed as a sequence of operations. It is mainly a paper of our research on the techniques of Boolean function manipulation using Binary Decision Diagram(BDDs) and their applications for VLSI CAD System. In many practical applications related to digital system design, it is a basic technique to use ternary-valued functions. In this paper, we discuss the methods for representing logical values.

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A Fast Distributed Video Decoding by Parity Bit Request Estimation Using Rate-Distortion Model (패리티 비트 요구량 예측에 대한 율-왜곡 모델을 이용한 고속 분산 비디오 복호화)

  • Kim, Man-Jae;Kim, Jin-Soo;Kim, Joe-Gon;Lee, Si-Woong;Choi, Haechul
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2012.07a
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    • pp.328-329
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    • 2012
  • 분산 비디오 복호화 기술은 저 용량 저 전력 시스템을 위한 초경량 복호화기를 제공할 수 있어 최근 많은 이슈가 되고 있다. 그러나 분산 비디오 복호화 기술은 피드백 채널을 이용하여 반복적인 패리티 비트 제어 방법을 주로 사용하기 때문에 전체 복호화 시간이 매우 길다는 단점을 가지고 있다. 따라서 분산 비디오 복호화 시스템의 고속화가 반드시 필요하며 이를 위해 많은 연구가 진행되어 왔다. 본 논문에서는 분산 비디오 복호화의 고속화를 위하여 보조정보와 LDPCA 프레임의 율-왜곡을 이용하여 패리티 비트 요구량을 예측하는 방법을 제안한다. 모의실험을 통해 제안하는 방법을 이용함으로써 분산 비디오 복호화에 소요되는 전제 복호 시간 대비 약 80% 시간 절감 효과를 보인다.

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Estimating BP Decoding Performance of Moderate-Length Irregular LDPC Codes with Sphere Bounds

  • Chung, Kyu-Hyuk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.7C
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    • pp.594-597
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    • 2010
  • This paper estimates belief-propagation (BP) decoding performance of moderate-length irregular low-density parity-check (LDPC) codes with sphere bounds. We note that for moderate-length($10^3{\leq}N{\leq}4\times10^3$) irregular LDPC codes, BP decoding performance, which is much worse than maximum likelihood (ML) decoding performance, is well matched with one of loose upper bounds, i.e., sphere bounds. We introduce the sphere bounding technique for particular codes, not average bounds. The sphere bounding estimation technique is validated by simulation results. It is also shown that sphere bounds and BP decoding performance of irregular LDPC codes are very close at bit-error-rates (BERs) $P_b$ of practical importance($10^{-5}{\leq}P_b{\leq}10^{-4}$).

The Study of LDPC for Railroad Signal control system (철도 통신신호에서의 LDPC에 적용에 관한 연구)

  • Park, Joo-Yul;Kim, Hyo-Sang;Park, Tae-Ki;Kim, Bong-Taek;Chung, Ki-Seok
    • Proceedings of the KSR Conference
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    • 2009.05a
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    • pp.442-446
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    • 2009
  • As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Today, most of the railroad's controling communications between wayside and train are made in one way. Therefore, by using a forward error correction technique, which receiver can actively correct the signal error, we can increase the performance and the stability of the railroad signaling system. In this paper, we introduce low density parity check(LDPC) that is used by next generation wireless communications and DMB technique. We verified that we can achieve low bit error rate(BER) in high signal to noise ratio(SNR) by using LDPC.

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A Local Weight Learning Neural Network Architecture for Fast and Accurate Mapping (빠르고 정확한 변환을 위한 국부 가중치 학습 신경회로)

  • 이인숙;오세영
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.28B no.9
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    • pp.739-746
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    • 1991
  • This paper develops a modified multilayer perceptron architecture which speeds up learning as well as the net's mapping accuracy. In Phase I, a cluster partitioning algorithm like the Kohonen's self-organizing feature map or the leader clustering algorithm is used as the front end that determines the cluster to which the input data belongs. In Phase II, this cluster selects a subset of the hidden layer nodes that combines the input and outputs nodes into a subnet of the full scale backpropagation network. The proposed net has been applied to two mapping problems, one rather smooth and the other highly nonlinear. Namely, the inverse kinematic problem for a 3-link robot manipulator and the 5-bit parity mapping have been chosen as examples. The results demonstrate the proposed net's superior accuracy and convergence properties over the original backpropagation network or its existing improvement techniques.

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Enhanced Fuzzy Single Layer Perceptron

  • Chae, Gyoo-Yong;Eom, Sang-Hee;Kim, Kwang-Baek
    • Journal of information and communication convergence engineering
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    • v.2 no.1
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    • pp.36-39
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    • 2004
  • In this paper, a method of improving the learning speed and convergence rate is proposed to exploit the advantages of artificial neural networks and neuro-fuzzy systems. This method is applied to the XOR problem, n bit parity problem, which is used as the benchmark in the field of pattern recognition. The method is also applied to the recognition of digital image for practical image application. As a result of experiment, it does not always guarantee convergence. However, the network showed considerable improvement in learning time and has a high convergence rate. The proposed network can be extended to any number of layers. When we consider only the case of the single layer, the networks had the capability of high speed during the learning process and rapid processing on huge images.

High-Throughput QC-LDPC Decoder Architecture for Multi-Gigabit WPAN Systems (멀티-기가비트 WPAN 시스템을 위한 고속 QC-LDPC 복호기 구조)

  • Lee, Hanho;Ajaz, Sabooh
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.104-113
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    • 2013
  • A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.