• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.11
• /
• pp.1633-1640
• /
• 2013

In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.1
• /
• pp.93-102
• /
• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.4
• /
• pp.543-551
• /
• 2017

SOL (Short, Open and Load) calibration based on iterative error sensitivity is proposed in this paper. With advanced SOL calibration, unknown parasitic parameters at on-chip terminations are accurately estimated up to 20 GHz. Artificial terminations are designed on printed circuit board (PCB) to experiment the proposed method. On-chip SHORT, OPEN and LOAD fabricated inside silicon shows the accuracy of proposed calibration method through the comparison with known fixture S-parameter after de-embedding.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.1
• /
• pp.67-75
• /
• 2002

In this Paper, we discuss the PEEC method and construct the PEEC equivalent circuit of the test structure and construct the system matrix, which was simulated by numerical analysis. And we got node voltages and currents. Constructing the equivalent circuit, we extracted the parasitic parameter(R, L, C)using the simulator, which is based on finite element method, hence we could simulate the transient analysis.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.1
• /
• pp.12-20
• /
• 1997

Physical interconnect such as Printed Circuit Board(PCB) traces introduces new challenges for parameter extraction and delay calculation for high-speed system design. PCB traces are dominated by frequency dependent LC propagation which makes precharacterization difficult for all possible configurations. Moreover, simulating the transient behavior of the trace for noise and delay analysis requries the combined used of a variety of models and techniques for efficiently handling lossy, low-loss, frequency dependent, and coupled transmission lines together with lumped elements. In this paper we explain how the frequency dependence caused by ground plane proximity and skin effects can be modeled using the adstracted models. These abstracted (lumped) models are SPICE-compatible and can be simulated in time-domain, along with precharacterized lumped parasitic elements and nonlinear driver and load models.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.79-80
• /
• 2005

In this paper, the circuit models of optical to electrical(O/E) characteristics of waveguide photodiode(WGPD) submodule are examined. Test structures of WGPD and WGPD submodule were fabricated and S21 parameter was measured to characterize the O/E conversion property. Valid circuit models were derived by RF circuit simulation and O/E characteristics were modeled to analyze the effects of model parameters on the WGPD submodule performances. Based on the results, it can be concluded that the suggested WGPD submodule model can explain the characteristics of the O/E conversion of WGPD submodule, where the parasitic components originated from ribbon bonding block crucially influence on the performance of WGPD submodule, are able to show more efficient property by making compact bonding structure. We propose an effective WGPD submodule bonding structure and it can ensure the 40Gbps operation of WGPD.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.30 no.3
• /
• pp.181-189
• /
• 2019

In this study, a triple-band antenna that can be used in WLAN(Wireless Local Area Network) at 2.4 GHz, 5.8 GHz, and 5G at 3.5 GHz is fabricated. The proposed antenna uses a parasitic element to show the triple band, and the reflector is used at a distance of ${\lambda}/4$ from the antenna to reduce the Specific Absorption Rate(SAR). Its dimensions are $100{\times}75{\times}1.6mm^3$ and each parameter value is optimized for better performance and a lower SAR value. As a result, we obtained a bandwidth of 540 MHz(2.02~2.56 GHz), 390 MHz(3.39~3.78 GHz), and 1,210 MHz(5.56~6.77 GHz) based on the reflection loss factor of -10 dB. In addition, the SAR values of the antenna with reflector are observed to reduce below the SAR value of international standard.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.96-99
• /
• 2000

We presents a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and examined electrical parameters with a HP5475A TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3 $\times$ 3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, self inductance 146pH, mutual capacitance 10.9fF and mutual inductance 16.9pH. S parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55㎓ and the loss of 0.26dB. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.11
• /
• pp.62-69
• /
• 1998

The general degradation model has been applied to analyze the hot carrier induced degradation of the DC and RF characteristics of RF-nMOSFET. The degradation of cut-off frequency has been severer than the degradation of bulk MOSFET drain current. The value of the degradation rate n and the degradation parameter m for RF-nMOSFET has been equal to those for bulk MOSFET. The decrease of device degradation with the increase of fingers could be explained by the large source/drain parasitic resistance and drain saturation voltage. It has been also found that the RF performance degradation could be explained by the decrease of $g_{m}$ and $C_{gd}$ and the increase of $g_{ds}$ after stress. The degradation of the DC and RF characteristics of RF-nMOSFET could be predicted by the measurement of the substrate current.t.

• Journal of Electrical Engineering and Technology
• /
• v.8 no.5
• /
• pp.1182-1187
• /
• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.