• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.2
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• pp.1-9
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• 1997

For the reduction of parasitic inductance and matching of bonding wire in the package of microwave devices, we propose multiple bonding wires buried in a dielectric material of FR-4 composite. This structure is analyzed using the method of moments (MoM) and compared with the common bondwires and ribbon interconnections. The FR-4 composite is modelled by the cole-cole model which can consider the loss and the variation of the permittivity in a frequency. At 20 GHz, the parasitic reactance is reduced by 90%, 80%, 60% compared to those of a single bonding wire in air, double bonding wires in air and ribbon interconnection in air, respectively. Also, the new bondwire shows very good matching of 60.ohm characteristic impedance and has 15dB, 10dB, 5dB improvement of the return loss and 2.5dB, 0.7dB, 0.2dB improvement of the insertion loss compared to the common interconnections. This technique can minimize the parasitic effect of bondwires in microwave device packaging.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.201-206
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• 2019

This study presents the design and experimental result of a GaN-based DC-DC converter with an integrated gate driver. The GaN device is attractive to power electronic applications due to its superior device performance. However, the switching loss of a GaN-based power converter is susceptible to the common source inductance, and converter efficiency is severely degraded with a large loop inductance. The objective of this study is to achieve high-efficiency power conversion and the highest power density using a multiphase integrated half-bridge GaN solution with minimized loop inductance. Before designing the converter, several GaN and Si devices were compared and loss analysis was conducted. Moreover, the impact of common source inductance from layout parasitic inductance was carefully investigated. Experimental test was conducted in buck mode operation at 48 -12 V, and results showed a peak efficiency of 97.8%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.16-25
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• 2002

This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.

• Journal of electromagnetic engineering and science
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• v.12 no.2
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• pp.185-188
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• 2012

A compact monopole antenna possessing triple resonance ($f_1$, $f_2$, $f_3$) characteristics for (USB) dongle applications is presented. The resonance characteristic $f_1$ is determined by the overall length of the antenna. The monopole antenna acts as the main radiator for $f_3$ as well as the coupling feeding structure for the parasitic resonators in $f_1$, $f_2$. The resonance characteristic $f_2$ is achieved by a combination of the capacitance formed by the coupling between the top and bottom parasitic substrate resonators and the inductance generated by a via bridging the two parasitic resonators.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1413-1428
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• 2019

In this paper, a novel zero-voltage and zero-current switching (ZVZCS) interleaved two switch forward converter is proposed. By using a coupled-inductor-type smoothing filter, a snubber capacitor, the parallel capacitance of the leading switches and the transformer parasitic inductance, the proposed converter can realize soft-switching for the main power switches. This converter can effectively reduce the primary circulating current loss by using the coupled inductor and the snubber capacitor. Furthermore, this converter can reduce the reverse recovery loss, parasitic ringing and transient voltage stress in the secondary rectifier diodes caused by the leakage inductors of the transformer and the coupled inductance. The operation principle and steady state characteristics of the converter are analyzed according to the equivalent circuits in different operation modes. The practical effectiveness of the proposed converter was is illustrated by simulation and experimental results via a 500W, 100 kHz prototype using the power MOSFET.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.4
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• pp.356-363
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• 2016

The design methodology of an adequate input voltage and magnetizing inductance to minimize reactive power is suggested to design a wireless power transfer (WPT) converter for high-power transfer efficiency. To increase the magnetizing inductance, the turn number of the WPT coil is increased, thus causing high parasitic resistance in the WPT coil. Moreover, the high coil resistance produces high conduction loss in the transfer and receive coils. Therefore, the analysis of conduction loss is used in the design of the WPT coil and the operating point of the WPT converter. To verify the proposed design methodology, the mathematical analysis of the conduction loss is presented by experimental results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.216-222
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• 1996

Since many typical 2.5 Gbps optical transmitter modules use a 50$\Omega$ characteristic impedance, they require relatively high voltage and high power sources compared to the 25$\Omega$ module. However, simple replacement of the 50$\Omega$ internal matching impedance with 25$\Omega$ results in bandwidth reduction and consequent problem of data transmitter module is proposed in order to expand the modulator bandwidth. From the calculated resutls based on accurate 3-dimensional inductance analysis, we have found that the series parasitic inductance is a dominant element limiting the bandwidth and the insertion of a 2.5pF capacitor in parallel to the 20$\Omega$ matching resiter can increase the 3 dB bandwidth about 1.4GHz wider. The time-domain results show the rise time (140 psec) without the compensation is greatly improved to 63 psec with the compensation. This capacitive ocmpensation can be implemented easily and be compatible with common manufacturing process of the optical transmitter module.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.98-105
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• 1995

Recent microwave IC's reach to the extent of high operating frequencies at which bonding wires limit their performance as dominant parasitic components. Double bonding wires separated by an internal angle have been firstly characterized using the Method of Moments with the incorporation of the ohmic resistance calculated by the phenomenological loss equivalence method. For a 30$^{\circ}$ internal angle, the calculated total reactance is 45% less than that of a single bonding wire due to the negative mutual coupling effect. The radiation effect has been observed decreasing the mutual inductance, whereas for parallel bonding wires it greatly increases the mutual inductance. This calculation results can be widely used for designing and packaging of high frequency and high density MMIC's and OEIC's.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.939-940
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• 2006

An integrated inductor using the low-temperature co-fired ceramics(LTCC ) technology for low-power electronics was fabricated. In the inductor NiZn ferrite sheet(${\mu}_r=230$), was embedded to increase inductance. The inductor has Ag spiral coil with 14 turns($7turns{\times}2layers$), a dimension of 0.6mm in width, 10um in thickness, and 0.15mm pitch. To evaluate the inductance, including the parasitic resistance, the fabricated inductor was calculated and measured. It was confirmed that calculated values were very close to the measured values. Finally as an application of the LTCC integrated inductor to low power electronic circuits, a LTCC buck DC/DC converter with 1W output power and up to 0.5MHz switching frequency using the inductor fabricated was develop.