• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.20-32
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• 1997

An optimum parasitic inductance is observed for maximizing the modulation bandwidth of the multiple quantum well (MQW) electro-absorption optical modulator. For 1.1 pF device cpaacitance of the current MQW optical modulator, the optimum parasitic inductances for maximum bandwidth are calculated for different terminating resistors. In ase of 50.ohm. terminating resistor, the 3-dB modulation bandwidth can be increased 45% wider by using the optimum parasitic inductance than nothing parasitic inductance. This calculated optimum inductance can be practically implemented, since the parasitic inductance of bondwires can be accurately analyzed using the method of moments (MoM) and controlled by changing the length and shpae of bondwires.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.195-203
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• 2020

This paper presents a parasitic inductance reduction design method for the stable driving of GaN HEMT. To reduce the parasitic inductance, we propose a vertical lattice loop structure with multiple loops that is not affected by the GaN HEMT package. The proposed vertical lattice loop structure selects the reference loop and designs the same loop as the reference loop by layering. The design reverses the current direction of adjacent current paths, increasing magnetic flux cancellation to reduce parasitic inductance. In this study, we validate the effectiveness of the parasitic inductance reduction method of the proposed vertical lattice loop structure.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.2
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• pp.117-122
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• 2013

The distributed power conversion LED driver circuit using parasitic inductance is proposed in this paper. while the conventional LED driver circuit is composed of the large size devices and heatsinks, the proposed circuit can be realized with the small sized no heatsink based. since the processing power can be effectively distributed. Also by using the wire parasitic inductance of the LED string, the proposed circuit can be implemented without external magnetic device. As a result, the proposed circuit which features the small size and volume con be realized even without LED driver module(LDM) board. since, all the device can be attached to the existing LED array Module(LAM) board. Therefore, it features that cost savings and volume reduction of circuit. To confirm the validity of the proposed circuit, theoretical analysis and experimental results from a distributed power conversion LED driver circuit prototype are presented.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.148-162
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• 1996

Bonding wires for high frequency device packaging have dominant parasitic inductances which limit the performance of semiconductor lasers. In this paper, the inductance sof bonding wires are claculated by the method of moments with incorporation of ohmic loss, and the wideband modulation characteristics are analyzed for ddifferent wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire is 7 GHz wider than that for 2mm-length bonding wire. We also observed th estatic inductance calculation results in dispersive deviation of the parasitic inductance and the modulation characteristics from the wideband moment methods calculations. The angled bonding wire has much less parasitic inductance and improves the modulation bandwidth more than 6 GHz. This calculation resutls an be widely used for designing and packaging of high-speed semiconductor device.

• ETRI Journal
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• v.38 no.1
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• Journal of Power Electronics
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• v.18 no.3
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• pp.892-901
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• 2018

SiC MOSFETs have been used to improve system efficiency in high frequency converters due to their extremely high switching speed. However, this can result in undesirable parasitic oscillations in practical systems. In this paper, models of the key components are introduced first. Then, theoretical formulas are derived to calculate the switching oscillation frequencies after full turn-on and turn-off in clamped inductive circuits. Analysis indicates that the turn-on oscillation frequency depends on the power loop parasitic inductance and parasitic capacitances of the freewheeling diode and load inductor. On the other hand, the turn-off oscillation frequency is found to be determined by the output parasitic capacitance of the SiC MOSFET and power loop parasitic inductance. Moreover, the shifting regularity of the turn-off maximum peak voltage with a varying switching speed is investigated on the basis of time domain simulation. The distortion of the turn-on current is theoretically analyzed. Finally, experimental results verifying the above calculations and analyses are presented.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.459-465
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• 2017

In this paper, we introduce the design consideration of the lightning induced transient protection circuit for the indirect lightning strike on the avionics equipment. The lightning induced surge voltage, which is so-called as indirect effects of lightning, may cause a functional failure or physical damage to the electrical and electronic equipment of aircraft. In order to protect the electrical and electronic equipment of aircraft from the indirect effects of lightning, we should analyze the effect of lightning strike on aircraft and consider applying protection design for each avionics device. However, lightning induced transient protection circuits can have unintended consequences because parasitic inductance elements are exist in PCB and TVS diodes. In this paper, we introduce the design method of the protection circuit considering the parasitic inductance of the protection circuit. In addition, we show the result of verification test performed to validate the protection circuits for indirect effects of lightning.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.899-902
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• 2003

Chip Pin Parasitic은 실제 Chip Pad에서부터 Bonding Wire를 통한 Package Lead Frame까지를 의미한다. 여기서, Lead Frame 및 Bonding Wire에서 Inductance 및 작은 저항이 보이고, Chip Pad에서의 Capacitance, 그리고 Pad 부터 Ground까지의 Return Path에서 발생하는 저항이 보인다. 이들을 모두 합하면 L, R, C의 Series로 나타낼 수 있다. 본 논문에서는 이런 Chip Pin Parasitic을 추출 하기 위해서 TDR(Time Domain Reflectometer)과 NA(Network Analyzer)를 사용하였는데, TDR의 경우 PCB를 제작하여 Chip을 Board위에 붙인 후 Time Domain에서 측정 하였고 NA의 경우 Pico Probe를 이용하여 Chip pin에 직접 Probing해서 Smith Chart를 통하여 Extraction 값을 추출했다. 이 경우, NA를 이용한 측정이 좀 더 정확한 Parasitic 값을 추출할 수 있으리라 예상되겠지만, 실제로 Chip이 구동하기 위해서는 Board위에 있을 때의 상황도 고려해야 하기 때문에 TDR 추출 값과 NA 추출 값을 모두 비교하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.5
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.