The Transactions of the Korean Institute of Power Electronics (전력전자학회논문지)

The Korean Institute of Power Electronics (전력전자학회)
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Parasitic Inductance Reduction Design Method of Vertical Lattice Loop Structure for Stable Driving of GaN HEMT

GaN HEMT의 안정적 구동을 위한 수직 격자 루프 구조의 기생 인덕턴스 저감 설계 기법

  • Yang, Si-Seok (Dept. of Electrical Engineering, HYPEC-EPECS Lab., Hanyang University) ;
  • Soh, Jae-Hwan (Dept. of Electrical Engineering, HYPEC-EPECS Lab., Hanyang University) ;
  • Min, Sung-Soo (Dept. of Electrical Engineering, HYPEC-EPECS Lab., Hanyang University) ;
  • Kim, Rae-Young (Dept. of Electrical Bio-Engineering, Hangyang University)
  • Received : 2019.12.23
  • Accepted : 2020.02.24
  • Published : 2020.06.20
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Abstract

This paper presents a parasitic inductance reduction design method for the stable driving of GaN HEMT. To reduce the parasitic inductance, we propose a vertical lattice loop structure with multiple loops that is not affected by the GaN HEMT package. The proposed vertical lattice loop structure selects the reference loop and designs the same loop as the reference loop by layering. The design reverses the current direction of adjacent current paths, increasing magnetic flux cancellation to reduce parasitic inductance. In this study, we validate the effectiveness of the parasitic inductance reduction method of the proposed vertical lattice loop structure.

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References

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