• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.269-270
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• 2015

본 논문에서는 GaN FET과 같이 고주파 스위칭이 가능하나 턴-온 문턱전압이 매우 낮은 전력반도체 소자의 안정적 구동을 위해 기생성분을 최소화 할 수 있는 PCB Layout 설계 방법에 대해 고찰한다. PCB Track의 길이 및 배치에 따른 기생 인덕턴스 등의 기생성분을 정량적으로 분석하고, Faulty 턴-온에 가장 직접적인 문제를 야기하는 ac-loop 인덕턴스 최소화 설계 방법을 제시하며 실험으로 검증한다.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.577-579
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• 2004

Digital hearing aids enclose $6{\sim}8$ tiny components. Those electromechanical components are individually wired by soldering which is a manual labor and sometimes causes components' damage by heating. This paper suggests a PCB design for overcome these problems. Several PCBs are designed and manufactured and circuited to produce ITE(In The Ear) type hearing aids which are inserted in the ear canal. The most optimal size of the PCB design for the ITE hearing aid is presented in this paper.

• Proceedings of the KSME Conference
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• 2004.11a
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• pp.1012-1015
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• 2004

Digital hearing aids enclose $6{\sim}8$ tiny components. Those electromechanical components are individually wired by soldering which is a manual labor and sometimes causes components' damage by heating. This paper suggests a PCB design for overcome these problems. Several PCBs are designed and manufactured and circuited to produce ITE(In-the-Ear) type hearing aids which are inserted in the ear canal. The most optimal size of the PCB design for the ITE hearing aid is presented in this paper.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.1
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• pp.111-116
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• 2001

A practical scheme to reduce failure of the PCB(Printed Circuit Board) of a monitor is introduced using deformed mode shape under mechanical shock. When the monitor is given critical shock loads, cracks are commonly initiated at the tip of a hole on the PCB. Accordingly, a deformed mode shape of the PCB is obtained using a FEM code to define a weak point on the PCB under mechanical shock, and then the position and direction of the hole is determined to prevent the failure at the critical mode shape. Also, the stress intensity factor around the weak point on the PCB is calculated to check the possibility of fracture by normal tensile stress. In conclusion, present research is useful to assist the practical design of components-layout on the PCB.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.1
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• pp.436-440
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• 2014

To verity the effect of PCB plane layer to the output characteristics of the Switched Mode Power Supply (SMPS), this paper compared with a generic one-layer PCB and a double-side PCB. This paper specially focused on the voltage, the current and the high frequency noise of the output characteristic of the SMPS, using a double-side PCB which has same layout and was installed a ground plane on the opposite side. This double-side PCB was assembled by all same components which used on the SMPS using the single-side PCB. The experiment results show the SMPS using the ground plan PCB can efficiently reduce the high frequency noise to 50mV at 100MHz from 150mV in the single-side PCB. And the results also show the high harmonics frequency was reduced as well.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.6
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• pp.1115-1122
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• 2003

In this paper we fabricated microchip antenna operating in bluetooth frequency bands(2.402∼2.480GHz). The antenna has a size of about 54mm${\times}419mm${\times}40.8mm, giving a total bluetooth PCB for support and chip of about 11mm${\times}44mm${\times}41.6mm. Bandwidth of the designed and fabricated chip antenna for bruetooth is 10.71 % at the resonated frequency of 2.45GHz and the resonant frequency and bandwidth versus change of any arbitrary feed point is observed. also, E-plane and H-plane in the Measured radiation pattern characteristic of chip antenna is compared and analyzed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.639-643
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• 2018

As electronic systems become smaller and more portable, the need for power conversion continues to increase. In addition, system stability must be ensured from switching noise due to power conversion efficiency and power conversion system miniaturization. Therefore, countermeasures to reduce switching noise during power conversion are essential. In this paper, a DC/DC buck converter circuit is constructed, and the characteristics of switching noise generated when changing the parts layout in a four-layer printed circuit board (PCB) structure with a reference plane are compared and analyzed. In addition, switching noise characteristics were compared and analyzed through simulations when the parts layout was different in a two-layer PCB structure from which the reference planes were removed. As a result, it was confirmed that the radiated emissions characteristic is reduced by 12dB and the conducted emissions characteristic decreased by 7dB to 8dB, according to the current return path in the four-layer PCB structure. Thus, it was confirmed that the noise characteristics can be improved according to the configuration of the current return path when the power conversion circuit is designed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.681-684
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• 2008

In this paper, triple band mobile chip antenna for DCS($1.71{\sim}1.88GHz$) / PCS($1.75{\sim}1.87GHz$) / UPCS($1.85{\sim}1.99GHz$) on PCB Layout is fabricated. As designed and fabricated antenna is loaded PCB layout, that plate a both side at two independence patterns(upper & lower) to reduce the size and a capacitor for DCS, PCS, UPCS band is proposed. The antenna has a small size of about $19mm{\times}4mm{\times}1.6mm$, narrow bandwidth which is the defect of chip antenna is improved. Bandwidth of fabricated antenna to VSWR less than 2 is satisfied and all bandwith is acquired 15.1 % at $1.71GHz{\sim}1.99GHz$.

• KIPE Magazine
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• v.25 no.4
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• pp.35-38
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• 2020

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.